Product data
UJA1167 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 18 April 2014 45 of 60
NXP Semiconductors
UJA1167
Mini high-speed CAN system basis chip with Standby/Sleep modes &
watchdog
10. Dynamic characteristics
Table 47. Dynamic characteristics
T
vj
=
40
C to +150
C; V
BAT
= 3 V to 28 V; R
(CANH-CANL)
= 60
; all voltages are defined with respect to ground; positive
currents flow into the IC; typical values are given at V
BAT
= 13 V; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Voltage source; pin V1
t
startup
start-up time from V
BAT
exceeding the
power-on detection threshold
until V
V1
exceeds the 90 %
undervoltage threshold;
C
V1
=4.7F
-2.84.7ms
t
d(uvd)
undervoltage detection delay time 6 - 54 s
t
d(uvd-RSTNL)
delay time from undervoltage
detection to RSTN LOW
undervoltage on V1 - - 63 s
t
d(buswake-VOH)
delay time from bus wake-up to
HIGH-level output voltage
HIGH = 0.8V
O(V1)
;
I
V1
100 mA
--5ms
Voltage source; pin VEXT
t
d(uvd)
undervoltage detection delay time 6 - 39 s
t
d(ovd)
overvoltage detection delay time 6 - 39 s
Serial peripheral interface timing; pins SCSN, SCK, SDI and SDO
t
cy(clk)
clock cycle time 250 - - ns
t
SPILEAD
SPI enable lead time 50 - - ns
t
SPILAG
SPI enable lag time 50 - - ns
t
clk(H)
clock HIGH time 125 - - ns
t
clk(L)
clock LOW time 125 - - ns
t
su(D)
data input set-up time 50 - - ns
t
h(D)
data input hold time 50 - - ns
t
v(Q)
data output valid time pin SDO; C
L
= 20 pF - - 50 ns
t
WH(S)
chip select pulse width HIGH pin SCSN 250 - - ns
t
to(SPI)
SPI time-out time after leaving Reset mode - - 40 s
CAN transceiver timing; pins CANH, CANL, TXD and RXD
t
d(TXD-RXD)
delay time from TXD to RXD R
L
=60; C
L
= 100 pF;
50 % V
TXD
to 50 % V
RXD
;
C
RXD
= 15 pF;
f
TXD
= 250 kHz
--255ns
R
L
= 120 ; C
L
=200 pF;
50 % V
TXD
to 50 % V
RXD
;
C
RXD
= 15 pF;
f
TXD
= 250 kHz
[1]
--350ns
t
d(TXD-busdom)
delay time from TXD to bus
dominant
-80-ns
t
d(TXD-busrec)
delay time from TXD to bus
recessive
-80-ns
t
d(busdom-RXD)
delay time from bus dominant to
RXD
C
RXD
= 15 pF - 105 - ns