Product data

Product data sheet Rev. 2 — 18 April 2014 37 of 60

NXP Semiconductors

UJA1167

Mini high-speed CAN system basis chip with Standby/Sleep modes &

watchdog

6.15.3 Register configuration in UJA1167 operating modes

A number of register bits may change state automatically when the UJA1167 switches

from one operating mode to another. This is particularly evident when the UJA1167

switches to Off mode. These changes are summarized in Table 43

. If an SPI transmission

is in progress when the UJA1167 changes state, the transmission is ignored (automatic

state changes have priority).

Table 38. Overview of MTPNV status register

Address Register Name Bit:

7 6 5 4 3 2 1 0

0x70 MTPNV status WRCNTS ECCS NVMPS

Table 39. Overview of Startup control register

Address Register Name Bit:

7 6 5 4 3 2 1 0

0x73 Startup control reserved RLC VEXTSUC reserved

Table 40. Overview of SBC configuration control register

Address Register Name Bit:

7 6 5 4 3 2 1 0

0x74 SBC configuration control reserved V1RTSUC FNMC SDMC reserved SLPC

Table 41. Overview of CRC control register

Address Register Name Bit:

7 6 5 4 3 2 1 0

0x75 MTPNV CRC control CRCC[7:0]

Table 42. Overview of Identification register

Address Register Name Bit:

7 6 5 4 3 2 1 0

0x7E Identification IDS[7:0]

Table 43. Register bit settings in UJA1167 operating modes

Symbol Off (power-on

default)

Standby Normal Sleep Overtemp Reset

CBS 0 no change no change no change no change no change

CBSE 0 no change no change no change no change no change

CBSS 1 actual state actual state no change actual state actual state

CF 0 no change no change no change no change no change

CFE 0 no change no change no change no change no change

CFS 0 actual state actual state actual state actual state actual state

CMC 00 no change no change no change no change no change

CRCC 00000000 no change no change no change no change no change

CTS 0 0 actual state 0 0 0

CW 0 no change no change no change no change no change