Product data

Product data sheet Rev. 2 — 18 April 2014 35 of 60

NXP Semiconductors

UJA1167

Mini high-speed CAN system basis chip with Standby/Sleep modes &

watchdog

During an SPI data read or write operation, the contents of the addressed register(s) is

returned via pin SDO.

The UJA1167 tolerates attempts to write to registers that don't exist. If the available

address space is exceeded during a write operation, the data above the valid address

range is ignored (without generating an SPI failure event).

During a write operation, the UJA1167 monitors the number of SPI bits transmitted. If the

number recorded is not 16, 24 or 32, then the write operation is aborted and an SPI failure

event is captured (SPIF = 1).

If more than 32 bits are clocked in on pin SDI during a read operation, the data stream on

SDI is reflected on SDO from bit 33 onwards.

After the UJA1167 exits Reset mode (positive edge on RSTN), an SPI read/write access

must not be attempted for at least t

to(SPI)

. Any earlier access may be ignored (without

generating an SPI failure event).