Product data

UJA1167 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 18 April 2014 34 of 60
NXP Semiconductors
UJA1167
Mini high-speed CAN system basis chip with Standby/Sleep modes &
watchdog
The SPI data in the UJA1167 is stored in a number of dedicated 8-bit registers. Each
register is assigned a unique 7-bit address. Two bytes must be transmitted to the SBC for
a single register write operation. The first byte contains the 7-bit address along with a
‘read-only’ bit (the LSB). The read-only bit must be 0 to indicate a write operation (if this bit
is 1, a read operation is assumed and any data on the SDI pin is ignored). The second
byte contains the data to be written to the register.
24- and 32-bit read and write operations are also supported. The register address is
automatically incremented, once for a 24-bit operation and twice for a 32-bit operation, as
illustrated in Figure 9
.
Fig 8. SPI timing protocol
SCSN
SCK
01
sampled
floating floating
015aaa255
X
X
MSB MSB–1 MSB–2 MSB–3 01 LSB
MSB MSB–1 MSB–2 MSB–3 01 LSB
X
SDI
SDO
02 03 04 N–1 N
Fig 9. SPI data structure for a write operation (16-, 24- or 32-bit)
data byte 3
0x03 0x040x00 0x7F0x01 0x05 0x070x02 0x06 0x7D 0x7E
Register Address Range
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Data Bits
dataID=0x05 data data
Address Bits
A5 A4 A3 A2 A1 A0 ROA6
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Data Bits
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Data Bits
addr 0000101 data byte 1 data byte 2
015aaa289
Read-only Bit