Product data

Product data sheet Rev. 2 — 18 April 2014 33 of 60

NXP Semiconductors

UJA1167

Mini high-speed CAN system basis chip with Standby/Sleep modes &

watchdog

6.14 General purpose memory

UJA1167 allocates 4 bytes of RAM as general purpose registers for storing user

information. The general purpose registers can be accessed via the SPI at address 0x06

to 0x09 (see Table 34

6.15 SPI

6.15.1 Introduction

The Serial Peripheral Interface (SPI) provides the communication link with the

microcontroller, supporting multi-slave operations. The SPI is configured for full duplex

data transfer, so status information is returned when new control data is shifted in. The

interface also offers a read-only access option, allowing registers to be read back by the

application without changing the register content.

The SPI uses four interface signals for synchronization and data transfer:

• SCSN: SPI chip select; active LOW

• SCK: SPI clock; default level is LOW due to low-power concept (pull-down)

• SDI: SPI data input

• SDO: SPI data output; floating when pin SCSN is HIGH

Bit sampling is performed on the falling edge of the clock and data is shifted in/out on the

rising edge, as illustrated in Figure 8

2 LK2C R/W lock control 2: address area 0x20 to 0x2F - transceiver control

0 SPI write-access enabled

1 SPI write-access disabled

1 LK1C R/W lock control 1: address area 0x10 to 0x1F - regulator control

0 SPI write-access enabled

1 SPI write-access disabled

0 LK0C R/W lock control 0: address area 0x06 to 0x09 - general purpose

memory

0 SPI write-access enabled

1 SPI write-access disabled

Table 33. Lock control register (address 0Ah)

Bit Symbol Access Value Description