Product data

UJA1167 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 18 April 2014 30 of 60
NXP Semiconductors
UJA1167
Mini high-speed CAN system basis chip with Standby/Sleep modes &
watchdog
6.11.1 Programming MTPNV cells
The UJA1167 must be in Forced Normal mode and the MTPNV cells must contain the
factory preset values before the non-volatile memory can be reprogrammed. The
UJA1167 will switch to Forced Normal mode after a reset event (e.g. pin RSTN LOW)
when the MTPNV cells contain the factory preset values (since FNMC = 1).
The factory presets may need to be restored before reprogramming can begin (see
Section 6.11.2
). When the factory presets have been restored, a system reset is
generated automatically and UJA1167 switches to Forced Normal mode. This ensures
that the programming cycle cannot be interrupted by the watchdog.
Programming of the non-volatile memory registers is performed in two steps. First, the
required values are written to addresses 0x73 and 0x74. In the second step,
reprogramming is confirmed by writing the correct CRC value to the MTPNV CRC control
register (see Section 6.11.1.1
). The SBC starts reprogramming the MTPNV cells as soon
as the CRC value has been validated. If the CRC value is not correct, reprogramming is
aborted. On completion, a system reset is generated to indicate that the MTPNV cells
have been reprogrammed successfully. Note that the MTPNV cells cannot be read while
they are being reprogrammed.
After an MTPNV programming cycle has been completed, the non-volatile memory is
protected from being overwritten via a standard SPI write operation.
The MTPNV cells can be reprogrammed a maximum of 200 times (N
cy(W)MTP
; see
Table 46
). Bit NVMPS in the MTPNV status register (Table 29) indicates whether the
non-volatile cells can be reprogrammed. This register also contains a write counter,
WRCNTS, that is incremented each time the MTPNV cells are reprogrammed (up to a
maximum value of 111111; there is no overflow). Note that this counter is provided for
information purposes only; reprogramming will not be aborted if it reaches its maximum
value. An error correction code status bit, ECCS, indicates whether reprogramming was
successful.
[1] Factory preset value.
Table 28. Overview of MTPNV registers
Address Register Name Bit:
7 6 5 4 3 2 1 0
0x73 Start-up control
(see Table 11
)
reserved RLC VEXTSUC reserved
0x74 SBC configuration control
(see Table 8
)
reserved V1RTSUC FNMC SDMC reserved SLPC
Table 29. MTPNV status register (address 70h)
Bit Symbol Access Value Description
7:2 WRCNTS R xxxxxx write counter: contains the number of times the
MTPNV cells were reprogrammed
1 ECCS R 0 no error detected during MTPNV cell programming
1 an error was detected during MTPNV cell
programming
0 NVMPS R 0 MTPNV memory cannot be overwritten
1
[1]
MTPNV memory is ready to be reprogrammed