Product data

UJA1167 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 18 April 2014 29 of 60
NXP Semiconductors
UJA1167
Mini high-speed CAN system basis chip with Standby/Sleep modes &
watchdog
[1] UJA1167TK/VX only; reserved in the UJA1167TK.
6.11 Non-volatile SBC configuration
The UJA1167 contains Multiple Time Programmable Non-Volatile (MTPNV) memory cells
that allow some of the default device settings to be reconfigured. The MTPNV memory
address range is from 0x73 to 0x74. An overview of the MTPNV registers is given in
Table 28
.
Table 25. Supply event capture enable register (address 1Ch)
Bit Symbol Access Value Description
7:3 reserved R -
2 VEXTOE
[1]
R/W VEXT overvoltage detection:
0 VEXT overvoltage detection disabled
1 VEXT overvoltage detection enabled
1 VEXTUE
[1]
R/W VEXT undervoltage detection:
0 VEXT undervoltage detection disabled
1 VEXT undervoltage detection enabled
0 V1UE R/W V1 undervoltage detection:
0 V1 undervoltage detection disabled
1 V1 undervoltage detection enabled
Table 26. Transceiver event capture enable register (address 23h)
Bit Symbol Access Value Description
7:5 reserved R -
4 CBSE R/W CAN bus silence detection:
0 CAN bus silence detection disabled
1 CAN bus silence detection enabled
3:2 reserved R -
1 CFE R/W CAN failure detection
0 CAN failure detection disabled
1 CAN failure detection enabled
0 CWE R/W CAN wake-up detection:
0 CAN wake-up detection disabled
1 CAN wake-up detection enabled
Table 27. WAKE pin event capture enable register (address 4Ch)
Bit Symbol Access Value Description
7:2 reserved R -
1 WPRE R/W rising-edge detection on WAKE pin:
0 rising-edge detection on WAKE pin disabled
1 rising-edge detection on WAKE pin enabled
0 WPFE R/W falling-edge detection on WAKE pin:
0 falling-edge detection on WAKE pin disabled
1 falling-edge detection on WAKE pin enabled