Product data

UJA1167 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 18 April 2014 28 of 60
NXP Semiconductors
UJA1167
Mini high-speed CAN system basis chip with Standby/Sleep modes &
watchdog
[1] UJA1167TK/VX only; reserved in the UJA1167TK.
Table 21. Supply event status register (address 62h)
Bit Symbol Access Value Description
7:3 reserved R -
2 VEXTO
[1]
R/W 0 no VEXT overvoltage event captured
1 VEXT overvoltage event captured
1 VEXTU
[1]
R/W 0 no VEXT undervoltage event captured
1 VEXT undervoltage event captured
0 V1U R/W 0 no V1 undervoltage event captured
1 V1 undervoltage event captured
Table 22. Transceiver event status register (address 63h)
Bit Symbol Access Value Description
7:5 reserved R -
4 CBS R/W 0 CAN bus active
1 no activity on CAN bus for t
to(silence)
3:2 reserved R -
1 CF R/W 0 no CAN failure detected
1 CAN transceiver deactivated due to V1 undervoltage
OR dominant clamped TXD
0 CW R/W 0 no CAN wake-up event detected
1 CAN wake-up event detected while the transceiver is
in CAN Offline Mode
Table 23. WAKE pin event capture status register (address 64h)
Bit Symbol Access Value Description
7:2 reserved R -
1 WPR R/W 0 no rising edge detected on WAKE pin
1 rising edge detected on WAKE pin
0 WPF R/W 0 no falling edge detected on WAKE pin
1 falling edge detected on WAKE pin
Table 24. System event capture enable register (address 04h)
Bit Symbol Access Value Description
7:3 reserved R -
2 OTWE R/W overtemperature warning event capture:
0 overtemperature warning disabled
1 overtemperature warning enabled
1 SPIFE R/W SPI failure detection:
0 SPI failure detection disabled
1 SPI failure detection enabled
0 reserved R -