Product data

UJA1167 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 18 April 2014 27 of 60
NXP Semiconductors
UJA1167
Mini high-speed CAN system basis chip with Standby/Sleep modes &
watchdog
changes. At least one regular wake-up event must be enabled before the UJA1167 can
switch to Sleep mode. Any attempt to enter Sleep mode while all regular wake-up events
are disabled will trigger a system reset.
Another condition that must be satisfied before the UJA1167 can switch to Sleep mode is
that all event status bits must be cleared. If an event is pending when the SBC receives a
Sleep mode command (MC = 001), it will immediately switch to Reset mode. This
condition applies to both regular and diagnostic events.
Sleep mode can be permanently disabled in applications where, for safety reasons, the
supply voltage to the host controller must never be cut off. Sleep mode is permanently
disabled by setting the Sleep control bit (SLPC) in the SBC configuration register (see
Table 8
) to 1. This register is located in the non-volatile memory area of the device. When
SLPC = 1, a Sleep mode SPI command (MC = 001) will trigger an SPI failure event
instead of a transition to Sleep mode.
6.10.3 Event status and event capture registers
After an event source has been identified, the status flag should be cleared (set to
0) by writing 1 to the relevant status bit (writing 0 will have no effect).
Table 19. Global event status register (address 60h)
Bit Symbol Access Value Description
7:4 reserved R -
3 WPE R 0 no pending WAKE pin event
1 WAKE pin event pending at address 0x64
2 TRXE R 0 no pending transceiver event
1 transceiver event pending at address 0x63
1 SUPE R 0 no pending supply event
1 supply event pending at address 0x62
0 SYSE R 0 no pending system event
1 system event pending at address 0x61
Table 20. System event status register (address 61h)
Bit Symbol Access Value Description
7:5 reserved R -
4 PO R/W 0 no recent power-on
1 the UJA1167 has left Off mode after power-on
3 reserved R -
2 OTW R/W 0 overtemperature not detected
1 the global chip temperature has exceeded the
overtemperature warning threshold (T
th(warn)otp
)
1 SPIF R/W 0 no SPI failure detected
1 SPI failure detected
0 WDF R/W 0 no watchdog failure event captured
1 watchdog failure event captured