Product data

UJA1167 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 18 April 2014 26 of 60
NXP Semiconductors
UJA1167
Mini high-speed CAN system basis chip with Standby/Sleep modes &
watchdog
If an event occurs while the associated event capture function is enabled, the relevant
event status bit is set. If the transceiver is in CAN Offline mode with V1 active (SBC
Normal or Standby mode), pin RXD is forced LOW to indicate that a wake-up or interrupt
event has been detected. If the UJA1167 is in sleep mode when the event occurs, the
microcontroller supply, V1, is activated and the SBC switches to Standby mode (via Reset
mode).
The microcontroller can monitor events via the event status registers. An extra status
register, the Global event status register (Table 19
), is provided to help speed up software
polling routines. By polling the Global event status register, the microcontroller can quickly
determine the type of event captured (system, supply, transceiver or WAKE pin) and then
query the relevant table (Table 20
, Table 21, Table 22 or Table 23 respectively).
After the event source has been identified, the status flag should be cleared (set to 0) by
writing 1 to the relevant bit (writing 0 will have no effect). A number of status bits can be
cleared in a single write operation by writing 1 to all relevant bits.
It is strongly recommended to clear only the status bits that were set to 1 when the status
registers were last read. This precaution ensures that events triggered just before the
write access are not lost.
6.10.1 Interrupt/wake-up delay
If interrupt or wake-up events occur very frequently while the transceiver is in CAN Offline
mode, they can have a significant impact on the software processing time (because pin
RXD is repeatedly driven LOW, requiring a response from the microcontroller each time
an interrupt/wake-up is generated). The UJA1167 incorporates an event delay timer to
limit the disturbance to the software.
When one of the event capture status bits is cleared, pin RXD is released (HIGH) and a
timer is started. If further events occur while the timer is running, the relevant status bits
are set. If one or more events are pending when the timer expires after t
d(event)
, pin RXD
goes LOW again to alert the microcontroller.
In this way, the microcontroller is interrupted once to process a number of events rather
than several times to process individual events.
If all events are cleared while the timer is running, RXD remains HIGH after the timer
expires, since there are no pending events. The event capture registers can be read at
any time.
The event capture delay timer is stopped immediately when pin RSTN goes low (triggered
by a HIGH-to-LOW transition on the pin). RSTN is driven LOW when the SBC enters
Reset, Sleep, Overtemp and Off modes. A pending event is signaled on pin RXD when
the SBC enters Sleep mode.
6.10.2 Sleep mode protection
The wake-up event capture function is critical when the UJA1167 is in Sleep mode,
because the SBC will only leave Sleep mode in response to a captured wake-up event. To
avoid potential system deadlocks, the SBC distinguishes between regular and diagnostic
events (see Section 6.10
). Wake-up events (via the CAN bus or the WAKE pin) are
classified as regular events; diagnostic events signal failure/error conditions or state