Product data

UJA1167 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 18 April 2014 24 of 60
NXP Semiconductors
UJA1167
Mini high-speed CAN system basis chip with Standby/Sleep modes &
watchdog
6.8 CAN fail-safe features
6.8.1 TXD dominant timeout
A TXD dominant time-out timer is started when pin TXD is forced LOW while the
transceiver is in CAN Active Mode. If the LOW state on pin TXD persists for longer than
the TXD dominant time-out time (t
to(dom)TXD
), the transmitter is disabled, releasing the bus
lines to recessive state. This function prevents a hardware and/or software application
failure from driving the bus lines to a permanent dominant state (blocking all network
communications). The TXD dominant time-out timer is reset when pin TXD goes HIGH.
The TXD dominant time-out time also defines the minimum possible bit rate of 15 kbit/s.
When the TXD dominant time-out time is exceeded, a CAN failure event is captured
(CF = 1; see Table 22
), if enabled (CFE = 1; see Table 26). In addition, the status of the
TXD dominant timeout can be read via the CFS bit in the Transceiver status register
(Table 15
) and bit CTS is cleared.
6.8.2 Pull-up on TXD pin
Pin TXD has an internal pull-up towards V1 to ensure a safe defined recessive driver state
in case the pin is left floating.
6.8.3 V1 undervoltage event
A CAN failure event is captured (CF = 1), if enabled, when the supply to the CAN
transceiver (V1) falls below 90 % of its nominal value. In addition, status bit VCS is set
to 1.
6.8.4 Loss of power at pin BAT
A loss of power at pin BAT has no influence on the bus lines or on the microcontroller. No
reverse currents will flow from the bus.
6.9 Local wake-up via WAKE pin
Local wake-up is enabled via bits WPRE and WPFE in the WAKE pin event capture
enable register (see Table 27
). A wake-up event is triggered by a LOW-to-HIGH (if
WPRE = 1) and/or a HIGH-to-LOW (if WPFE = 1) transition on the WAKE pin. This
arrangement allows for maximum flexibility when designing a local wake-up circuit. In
applications that don’t make use of the local wake-up facility, local wake-up should be
disabled and the WAKE pin connected to GND to ensure optimal EMI performance.
While the SBC is in Normal mode, the status of the voltage on pin WAKE can always be
read via bit WPVS. Otherwise, WPVS is only valid if local wake-up is enabled (WPRE = 1
and/or WPFE = 1).
Table 16. WAKE status register (address 4Bh)
Bit Symbol Access Value Description
7:2 reserved R -
1 WPVS R WAKE pin status:
0 voltage on WAKE pin below switching threshold (V
th(sw)
)
1 voltage on WAKE pin above switching threshold (V
th(sw)
)
0 reserved R -