Product data

UJA1167 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 18 April 2014 23 of 60
NXP Semiconductors
UJA1167
Mini high-speed CAN system basis chip with Standby/Sleep modes &
watchdog
When a valid CAN wake-up pattern is detected on the bus, wake-up bit CW in the
Transceiver event status register is set (see Table 22
) and pin RXD is driven LOW. If the
SBC was in Sleep mode when the wake-up pattern was detected, V1 is enabled to supply
the microcontroller and the SBC switches to Standby mode via Reset mode.
6.7.3 CAN control and Transceiver status registers
[1] Only active when CMC = 01.
Fig 6. CAN wake-up timing
t
dom
≥ t
wake(busdom)
recessive
t
rec
≥ t
wake(busrec)
t
dom
≥ t
wake(busdom)
dominant dominant
015aaa267
t
wake
< t
to(wake)
CAN wake-up
Table 14. CAN control register (address 20h)
Bit Symbol Access Value Description
7:2 reserved R/W -
1:0 CMC R/W CAN transceiver operating mode selection (available
when UJA1167 is in Normal mode; MC = 111):
00 Offline mode
01 Active mode (when the SBC is in Normal mode);
V1/CAN undervoltage detection active
10 Active mode (when the SBC is in Normal mode);
V1/CAN undervoltage detection disabled
11 Listen-only mode
Table 15. Transceiver status register (address 22h)
Bit Symbol Access Value Description
7 CTS R 0 CAN transceiver not in Active mode
1 CAN transceiver in Active mode
6:4 reserved R -
3 CBSS R 0 CAN bus active (communication detected on bus)
1 CAN bus inactive (for longer than t
to(silence)
)
2 reserved R -
1VCS
[1]
R 0 the output voltage on V1 is above the 90 % threshold
1 the output voltage on V1 is below the 90 % threshold
0 CFS R 0 no TXD dominant timeout event detected
1 CAN transmitter disabled due to a TXD dominant
timeout event