Product data

UJA1167 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 18 April 2014 16 of 60
NXP Semiconductors
UJA1167
Mini high-speed CAN system basis chip with Standby/Sleep modes &
watchdog
6.3.2 Selecting the output reset pulse width
The duration of the output reset pulse is selected via bits RLC in the Start-up control
register (Table 11
). The SBC distinguishes between a cold start and a warm start. A cold
start is performed if the reset event was combined with a V1 undervoltage event
(power-on reset, reset during Sleep mode, over-temperature reset, V1 undervoltage
before entering or while in Reset mode). The output reset pulse width for a cold start is
determined by the setting of bits RLC.
If any other reset event occurs without a V1 undervoltage (external reset, watchdog
failure, watchdog change attempt in Normal mode, illegal Sleep mode command) the SBC
uses the shortest reset length (t
w(rst)
= 1 ms to 1.5 ms). This is called warm start of the
microcontroller.
[1] Factory preset value.
6.3.3 Reset sources
The following events will cause the UJA1167 to switch to Reset mode:
• V
V1
drops below the selected V1 undervoltage threshold defined by bits V1RTC
• pin RSTN is pulled down externally
• the watchdog overflows in Window mode
• the watchdog is triggered too early in Window mode (before t
trig(wd)1
)
• the watchdog overflows in Timeout mode with WDF = 1 (watchdog failure pending)
• an attempt is made to reconfigure the Watchdog control register while the SBC is in
Normal mode
• the SBC leaves Off mode
• local or CAN bus wake-up in Sleep mode
• diagnostic wake-up in Sleep mode
• the SBC leaves Overtemp mode
• illegal Sleep mode command received
Table 11. Start-up control register (address 73h)
Bit Symbol Access Value Description
7:6 reserved R -
5:4 RLC R/W RSTN output reset pulse width:
00
[1]
t
w(rst)
= 20 ms to 25 ms
01 t
w(rst)
= 10 ms to 12.5 ms
10 t
w(rst)
= 3.6 ms to 5 ms
11 t
w(rst)
= 1 ms to 1.5 ms
3 VEXTSUC R/W VEXT/INH start-up control:
0
[1]
bits VEXTC set to 00 at power-up
1 bits VEXTC set to 11 at power-up
2:0 reserved R -