Product data

Product data sheet Rev. 2 — 18 April 2014 15 of 60

NXP Semiconductors

UJA1167

Mini high-speed CAN system basis chip with Standby/Sleep modes &

watchdog

When the SBC is in Sleep mode with watchdog Timeout mode selected, a wake-up event

is generated after the nominal watchdog period (NWP). If bit WDF is set, RXD is forced

LOW and V1 is turned on. The application software can then clear the WDF bit and trigger

the watchdog before it overflows.

6.2.4 Watchdog behavior in Autonomous mode

Autonomous mode is selected when WMC = 001. In Autonomous mode, the watchdog is

either off or in Timeout mode, according to the conditions detailed in Table 10

When Autonomous mode is selected, the watchdog will be in Timeout mode if the SBC is

in Normal mode or Standby mode with RXD LOW, provided Software Development mode

has been disabled (SDMC = 0). Otherwise the watchdog will be off.

In Autonomous mode, the watchdog will not be running when the SBC is in Standby (RXD

HIGH) or Sleep mode. If a wake-up event is captured, pin RXD is forced LOW to signal

the event and the watchdog is automatically restarted in Timeout mode. If the SBC was in

Sleep mode when the wake-up event was captured, it switches to Standby mode.

6.3 System reset

When a system reset occurs, the SBC switches to Reset mode and initiates a process

that generates a low-level pulse on pin RSTN.

6.3.1 Characteristics of pin RSTN

Pin RSTN is a bidirectional open drain low side driver with integrated pull-up resistance,

as shown in Figure 4

. With this configuration, the SBC can detect the pin being pulled

down externally, e.g. by the microcontroller. The input reset pulse width must be at least

w(rst)

Table 10. Watchdog status in Autonomous mode

UJA1167 Operating mode Watchdog status

SDMC = 0 SDMC = 1

Normal Timeout mode off

Standby; RXD HIGH off off

Sleep off off

any other mode off off

Standby; RXD LOW Timeout mode off

Fig 4. RSTN internal pin configuration

RSTN

015aaa276