Product data

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Product data sheet Rev. 2 — 18 April 2014 14 of 60

NXP Semiconductors

UJA1167

Mini high-speed CAN system basis chip with Standby/Sleep modes &

watchdog

6.2.1 Software Development mode

Software Development mode is provided to simplify the software design process. When

Software Development mode is enabled, the watchdog starts up in Autonomous mode

(WMC = 001) and is inactive after a system reset, overriding the default value (see

Table 7

). The watchdog is always off in Autonomous mode if Software Development mode

is enabled (SDMC = 1; see Table 10

Software can be run without a watchdog in Software Development mode. However, it is

possible to activate and deactivate the watchdog for test purposes by selecting Window or

Timeout mode via bits WMC while the SBC is in Standby mode (note that Window mode

will only be activated when the SBC switches to Normal mode). Software Development

mode is activated via bits SDMC in non-volatile memory (see Table 8

6.2.2 Watchdog behavior in Window mode

The watchdog runs continuously in Window mode. The watchdog will be in Window mode

if WMC = 100 and the UJA1167 is in Normal mode.

In Window mode, the watchdog can only be triggered during the second half of the

watchdog period. If the watchdog overflows, or is triggered in the first half of the watchdog

period (before t

trig(wd)1

), a system reset is performed. After the system reset, the reset

source (either ‘watchdog triggered too early’ or ‘watchdog overflow’) can be read via the

reset source status bits (RSS) in the Main Status register (Table 5

). If the watchdog is

triggered in the second half of the watchdog period (after t

trig(wd)1

but before t

trig(wd)2

), the

watchdog timer is restarted.

6.2.3 Watchdog behavior in Timeout mode

The watchdog runs continuously in Timeout mode. The watchdog will be in Timeout mode

if WMC = 010 and the UJA1167 is in Normal, Standby or Sleep mode. The watchdog will

also be in Timeout mode if WMC = 100 and the UJA1167 is in Standby or Sleep mode. If

Autonomous mode is selected (WMC = 001), the watchdog will be in Timeout mode if one

of the conditions for Timeout mode listed in Table 10

has been satisfied.

In Timeout mode, the watchdog timer can be reset at any time by a watchdog trigger. If the

watchdog overflows, a watchdog failure event (WDF) is captured. If a WDF is already

pending when the watchdog overflows, a system reset is performed. In Timeout mode, the

watchdog can be used as a cyclic wake-up source for the microcontroller when the

UJA1167 is in Standby or Sleep mode. In Sleep mode, a watchdog overflow generates a

wake-up event.

1:0 WDS R watchdog status:

00 watchdog is off

01 watchdog is in first half of window

10 watchdog is in second half of window

11 reserved

Table 9. Watchdog status register (address 05h)

Bit Symbol Access Value Description