Product data

UJA1167 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 18 April 2014 13 of 60
NXP Semiconductors
UJA1167
Mini high-speed CAN system basis chip with Standby/Sleep modes &
watchdog
Two operating modes have a major impact on the operation of the watchdog: Forced
Normal mode and Software Development mode (Software Development mode is provided
for test purposes and is not an SBC operating mode; the UJA1167 can be in any mode
with Software Development mode enabled; see Section 6.2.1
). These modes are enabled
and disabled via bits FNMC and SDMC respectively in the SBC configuration control
register (see Table 8
). Note that this register is located in the non-volatile memory area
(see Section 6.10
). In Forced Normal mode (FNM), the watchdog is completely disabled.
In Software Development mode (SDM), the watchdog can be disabled or activated for test
purposes.
Information on the status of the watchdog is available from the Watchdog status register
(Table 9
). This register also indicates whether Forced Normal and Software Development
modes are active.
[1] Factory preset value.
Table 8. SBC configuration control register (address 74h)
Bit Symbol Access Value Description
7:6 reserved R -
5:4 V1RTSUC R/W V1 reset threshold (defined by bit V1RTC) at start-up:
00
[1]
V1 undervoltage detection at 90 % of nominal value at
start-up (V1RTC = 00)
01 V1 undervoltage detection at 80 % of nominal value at
start-up (V1RTC = 01)
10 V1 undervoltage detection at 70 % of nominal value at
start-up (V1RTC = 10)
11 V1 undervoltage detection at 60 % of nominal value at
start-up (V1RTC = 11)
3 FNMC R/W Forced Normal mode control:
0 Forced Normal mode disabled
1
[1]
Forced Normal mode enabled
2 SDMC R/W Software Development mode control:
0
[1]
Software Development mode disabled
1 Software Development mode enabled
1 reserved R -
0 SLPC R/W Sleep control:
0
[1]
the SBC supports Sleep mode
1 Sleep mode commands will be ignored
Table 9. Watchdog status register (address 05h)
Bit Symbol Access Value Description
7:4 reserved R -
3 FNMS R 0 SBC is not in Forced Normal mode
1 SBC is in Forced Normal mode
2 SDMS R 0 SBC is not in Software Development mode
1 SBC is in Software Development mode