Product data

UJA1167 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 18 April 2014 12 of 60
NXP Semiconductors
UJA1167
Mini high-speed CAN system basis chip with Standby/Sleep modes &
watchdog
A watchdog trigger event resets the watchdog timer. A watchdog trigger event is any valid
write access to the Watchdog control register. If the watchdog mode or the watchdog
period have changed as a result of the write access, the new values are immediately
valid.
[1] Default value if SDMC = 1 (see Section 6.2.1)
[2] Default value.
[3] Selected in Standby mode but only activated when the SBC switches to Normal mode.
The watchdog is a valuable safety mechanism, so it is critical that it is configured correctly.
Two features are provided to prevent watchdog parameters being changed by mistake:
• redundant states of configuration bits WMC and NWP
• reconfiguration protection in Normal mode
Redundant states associated with control bits WMC and NWP ensure that a single bit
error cannot cause the watchdog to be configured incorrectly (at least two bits must be
changed to reconfigure WMC or NWP). If an attempt is made to write an invalid code to
WMC or NWP (e.g. 011 or 1001 respectively), the SPI operation is abandoned and an SPI
failure event is captured, if enabled (see Section 6.10
).
Table 6. Summary of watchdog settings
Watchdog configuration via SPI
FNMC 000 0 1
SDMC xx0 1 x
WMC 100 (Window) 010 (Timeout) 001 (Autonomous) 001 (Autonomous) n.a.
Normal mode Window Timeout Timeout off off
SBC
Operating
Mode
Standby mode (RXD HIGH) Timeout Timeout off off off
Standby mode (RXD LOW) Timeout Timeout Timeout off off
Sleep mode Timeout Timeout off off off
Other modes off off off off off
Table 7. Watchdog control register (address 00h)
Bit Symbol Access Value Description
7:5 WMC R/W watchdog mode control:
001
[1]
Autonomous mode
010
[2]
Timeout mode
100
[3]
Window mode
4 reserved R -
3:0 NWP R/W nominal watchdog period
1000 8 ms
0001 16 ms
0010 32 ms
1011 64 ms
0100
[2]
128 ms
1101 256 ms
1110 1024 ms
0111 4096 ms