Datasheet
Data Sheet
©2013
Würth Elektronik eiSos GmbH & Co. KG - REV 0.2
PRELIMINARY
9/ 23
171020601/WPMDH1200601J
MagI³C Power Module Product Family
VDRM - Variable Step Down Regulator Module
J CIRCUIT DESCRIPTION
(2)
These resistors should be chosen from values in the range of 1kΩ to 50kΩ.
A feed-forward capacitor is placed in parallel with R
FBT
to improve load step transient response. Its value is usually
determined experimentally by load stepping between DCM and CCM conduction modes and adjusting for best
transient response and minimum output ripple.
A table of values for R
FBT
, R
FBB
, and R
ON
is included in the applications circuit.
Step 3. Select Soft-Start Capacitor (C
SS
)
Programmable soft-start permits the regulator to slowly ramp to its steady state operating point after being enabled,
thereby reducing current inrush from the input supply and slowing the output voltage rise-time to prevent overshoot.
Upon turn-on, after all UVLO conditions have been passed, an internal 8µA current source begins charging the
external soft-start capacitor. The soft-start capacitor can be calculated with: This equation can be rearranged as
follows:
(3)
with t
ss
= select soft-start time in (ms)
Use of a 0.022µF capacitor results in 2.2ms soft-start duration. This is a recommended value. Note that high values
of CSS capacitance will cause more output voltage droop when a load transient goes across the DCM-CCM
boundary. Use equation (15) below to find the DCM-CCM boundary load current for the specific operating condition. If
a fast load transient response is desired for steps between DCM and CCM mode the soft-start capacitor value should
be less than 0.018μF. Note that the following conditions will reset the soft-start capacitor by discharging the SS input
to ground with an internal 200μA current sink:
The enable input being “pulled low”
Thermal shutdown condition
Over-current fault
Internal V
IN
UVLO
Step 4. Select Output Capacitor (C
OUT
)
None of the required output capacitance is contained within the module. At a minimum, the output capacitor must
meet the worst case RMS current rating of
, as calculated in equation (16) below. Beyond that, additional
capacitance will reduce output ripple so long as the ESR is low enough to permit it. A minimum value of 10µF is
generally required. Experimentation will be required if attempting to operate with a minimum value. Low ESR
capacitors, such as ceramic and polymer electrolytic capacitors are recommended.
Capacitance:
The following equation provides a good first pass approximation of C
OUT
for load transient requirements:
(4)
For example:
Solving:
ESR:
The ESR of the output capacitor affects the output voltage ripple. High ESR will result in larger V
OUT
peak-to-peak
ripple voltage. Furthermore, high output voltage ripple caused by excessive ESR can trigger the over-voltage
protection monitored at the FB pin. The ESR should be chosen to satisfy the maximum desired V
OUT
peak-to-peak
ripple voltage and to avoid over-voltage protection during normal operation. The following equations can be used: