Specifications

Figure 3-2 illustrates the timing of all these operations and describes the
VT1419A’s input-update-execute algorithms-output phases. This cycle-based
design is desirable because it results in deterministic operation of the VT1419A.
That is, the input channels are always scanned and the output channels are always
written at pre-defined intervals. Note too that any number of input channels or
output channels are accessible by any of up to 32 user-written algorithms. The
algorithms are named ALG1-ALG32 and execute in numerical order.
Notice the Update Window (phase 2) illustrated in Figure 3-2. This window has a
user-specified length and is used to accept and make changes to local and global
variables from the supervisory computer. Up to 512 scalar or array changes can be
made while executing algorithms. Special care was taken to make sure all changes
take place at the same time so that any particular algorithm or group of algorithms
all operate on the new changes at a user-specified time. This does not mean that all
scalar and array changes have to be received during one cycle to become effective
at the next cycle. On the contrary, it may take a number of cycles to download new
values, especially when trying to re-write 1024 element arrays and especially when
the trigger cycle time is very short.
There are multiple times between the base triggers where scalar and array changes
can be accepted from the supervisory computer and these changes are held in a
holding buffer until the supervisory computer instructs the changes to take effect.
These changes then take place during the Update window and take effect BEFORE
algorithms start executing. The “do-update-now” signal can be sent by command
(ALG:UPD) or by a change in a digital input state (ALG:UPD:CHAN). In either
case, the programmer has control over when the new changes take effect.
Programming the VT1419A Multifunction
Plus
Overview of the VT1419A Multifunction
Plus
50 Chapter 3
Input Channels
Algorithm 1
Algorithm 2
Algorithm 3
Algorithm 4
Algorithm 5
O
utput Channels
Trigger Period
Output Delay Time
PHASE 1 (input)
PHASE 3 (execute algorithms)
PHASE 2
Update Variable Changes
Channel 0
Channel 32
Channel 1
Channel 33
Channel 2
Channel 34
Channel 7
Channel 35
Channel 16
Channel 36
PHASE 4 (output)
Channel 37
Channel 38
Figure 3-2: VT1419A Cycle Phases
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