Specifications

Comments
·
When using the Questionable Event register to cause SRQ interrupts,
STAT:QUES:EVENT? must be executed after an SRQ to clear the register and
re-enable future interrupts.
·
Returned Value: Decimal weighted sum of all set bits. The C-SCPI type is
uint16.
·
Cleared By: *CLS, power-on and by reading the register.
·
Related Commands: *STB?, SPOLL, STAT:QUES:COND?,
STAT:QUES:ENABLE, STAT:QUES:ENABLE?
Usage STAT:QUES:EVENT? Enter statement will return the value of bits set in
the Questionable Event register
STAT:QUES? Same as above
STATus:QUEStionable:NTRansition
STATus:QUEStionable:NTRansition <transition_mask> sets bits in the
Negative Transition Filter (NTF) register. When a bit in the NTF register is set to
one, the corresponding bit in the Condition register must change from a one to a
zero in order to set the corresponding bit in the Event register. When a bit in the
NTF register is zero, a negative transition of the Condition register bit will not
change the Event register bit.
Parameters
Parameter
Name
Parameter
Type
Range of
Values
Default
Units
transition_mask numeric (uint16) 0-32767 none
Comments
·
The <transition_mask> parameter may be sent as decimal, hex (#H), octal (#Q),
or binary (#B).
·
If both the STAT:QUES:PTR and STAT:QUES:NTR registers have a
corresponding bit set to one, any transition, positive or negative, will set the
corresponding bit in the Event register.
·
If neither the STAT:QUES:PTR or STAT:QUES:NTR registers have a
corresponding bit set to one, transitions from the Condition register will have no
effect on the Event register.
·
Related Commands: STAT:QUES:NTR?, STAT:QUES:PTR
·
Cleared By: STAT:PRESet and power-on.
·
*RST Condition: No change
Usage STAT:QUES:NTR 1024 When “FIFO Overflowed” bit goes false, set bit 10
in Status Questionable Event register.
VT1419A Command Reference
STATus
300 Chapter 6
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