Specifications

Memory 89
Memory
As a standard feature, all Matrox Solios boards except Matrox Solios eCL/XCL-B
and Matrox Solios eCL/XCL-F support up to 256 Mbytes of linearly addressable,
DDR SDRAM used as acquisition memory. This memory has a bandwidth of up
to 1.6 Gbytes/sec when the optional Processing FPGA is installed, and up to
1.32 Gbytes/sec without the optional Processing FPGA installed.
As a standard feature, Matrox Solios eCL/XCL-B and eCL/XCL-F also support
acquisition memory. However, Matrox Solios eCL/XCL-B supports up to
128 Mbytes of linearly addressable DDR SDRAM, with a bandwidth of up to
800 Mbytes/sec. Matrox Solios eCL/XCL-F supports up to 256 Mbytes of
110 MHz SDRAM with a bandwidth of 1.76 Gbytes.
Optional memory If the optional Processing FPGA is installed on the board, Matrox Solios supports
up to 256 Mbytes of additional DDR SDRAM and either four or eight Mbytes
of QDRII SRAM. The Processing FPGA has an 83.3 MHz 64-bit DDR controller
and an 83.3 MHz 32-bit QDRII controller, for data transfer rates of
1.33 Gbytes/sec and 1.33 Gbytes/sec (666 Mbyte/sec input and 666 Mbyte/sec
output), respectively.
By default, some acquisition memory is mapped onto the PCI bus so that you can
use a Host pointer to access this memory, or you can access it directly from another
PCI/PCI-X bus master; this memory is referred to as shared memory. To allocate
a buffer in shared memory, use the MIL-Lite function MbufAlloc...() with
M_SHARED. To increase or decrease the amount of shared memory, use the
MilConfig utility. If your application accesses multiple boards that have their
memory mapped onto the PCI bus, ensure that the total amount of memory
mapped onto the PCI bus does not exceed the maximum address space available
to your application.