Specifications

Processing FPGA 85
Processing FPGA
To reduce the number of image processing tasks the Host CPU has to do, most
Matrox Solios boards can be purchased with the optional Processing FPGA. This
option is not supported on Matrox Solios eA/XA Single, eCL/XCL-B, or the
standard Camera Link speed (66 MHz) version of Matrox Solios eCL/XCL
dual-Base/single-Medium.
The optional Processing FPGA is based on the Altera Stratix family of
pin-compatible FPGA devices, and it can be programmed to perform operations
that satisfy your application’s needs (for example, to perform a Bayer conversion).
Possible processing operations
To use the Processing FPGA, you must configure it with an FPGA configuration
that defines the appropriate functionality. An FPGA configuration is a code
segment that is used to program an FPGA. You can use standard Matrox FPGA
configurations or you can create your own using the Matrox FPGA Developer’s
Toolkit (FDK) for Matrox Solios. Once the Processing FPGA is programmed, you
can then make use of its functionality using MIL. Refer to Using MIL with a
Processing FPGA chapter in the MIL User Guide for more information.
Processing
FPGA
QDRII
SRAM
(4/8 MB)
DDR SDRAM
(64/128/256 MB)
Optional
32
32
Video to
PCI-X Bridge
To Host
16
16
64
64