Specifications

80 Chapter 4: Matrox Solios hardware reference
Typ e of signa l
Acquisition Path Max # signals
*
TTL/LVDS dedicated
input/output signals
†
TTL/LVDS aux. input
‡
TTL/LVDS aux. output
‡
LVDS/TTL_AUX_IN0 LVDS/TTL_AUX_IN1 LVDS/TTL_AUX_IN2 LVDS/TTL_AUX_IN3 LVDS/TTL_AUX_IN4 LVDS/TTL_AUX_IN5 LVDS/TTL_AUX_IN6 LVDS/TTL_AUX_IN7 P0_LVDS/TTL_AUX_OUT0 P0_LVDS/TTL_AUX_OUT1 P1_LVDS/TTL_AUX_OUT0 P1_LVDS/TTL_AUX_OUT1 P2_LVDS/TTL_AUX_OUT0 P2_LVDS/TTL_AUX_OUT1 P3_LVDS/TTL_AUX_OUT0 P3_LVDS/TTL_AUX_OUT1
VSYNC 0 1 in +1 out P0_LVDS_TTL_VSYNC_IO in out
1 1 in + 1 out P1_LVDS_TTL_VSYNC_IO in out
2 1 in + 1 out P2_LVDS_TTL_VSYNC_IO in out
3 1 in + 1 out P3_LVDS_TTL_VSYNC_IO in out
CSYNC or
HSYNC
**
0 1 in + 1 out P0_LVDS/TTL_CHSYNC_IO in out
1 1 in + 1 out P1_LVDS/TTL_CHSYNC_IO in out
2 1 in + 1 out P2_LVDS/TTL_CHSYNC_IO in out
3 1 in + 1 out P3_LVDS/TTL_CHSYNC_IO in out
Clock 01 in/out P0_LVDS/TTL_CLK_IO
11 in/out P1_LVDS/TTL_CLK_IO
21 in/out P2_LVDS/TTL_CLK_IO
31 in/out P3_LVDS/TTL_CLK_IO
*. The maximum # for each signal type cannot always be attained. The actual maximum depends on whether the required auxiliary signals are
available or have been defined as another type.
†. In this column, each signal is a dedicated signal (that is, it cannot be redefined as another type of signal). These signals can be accessed from
the DVI connectors; the clock signal can also be accessed from the internal auxiliary I/O connector.
‡. On external auxiliary I/O connector 0 (DBHD-44).
**. The board can accept an HSYNC or CSYNC input signal, but it can only output an HSYNC signal.