Specifications

78 Chapter 4: Matrox Solios hardware reference
Synchronization, timing, and control signals
The following tables summarize the synchronization, timing, and control signals
supported by Matrox Solios eA/XA. Most of these signals are available by defining
an auxiliary (multi-purpose) signal as the required synchronization, timing, or
control signal. For example, P0_TTL_AUX(TRIG)_IN can be defined for
acquisition path 0 as a trigger input (trigger controller 0), field polarity input, and
user input signal.
Only the auxiliary signals of the first acquisition path used by a video source are
available (for example, if grabbing RGB and monochrome, only the auxiliary
signals for path 0 and path 3 are available).
Note that only signals defined for acquisition path 0 (those beginning with P0)
and the common LVDS/TTL auxiliary signals apply to the Matrox Solios eA/XA
Single board. Only signals defined for acquisition paths 0 and 1 and the common
LVDS/TTL signals apply to the Matrox Solios eA/XA Dual board.
You can set TTL/LVDS signals in pairs to either TTL or LVDS format when
accessed from the external auxiliary I/O connector 0 (DBHD-44) of the cable
adapter board. For example, setting LVDS/TTL_AUX_IN2 to TTL also sets
LVDS/TTL_AUX_IN3 to TTL, and setting P0_LVDS/TTL_AUX_OUT0 to
LVDS also sets P0_LVDS/TTL_AUX_OUT1 to LVDS.
TTL aux.
input
*
TTL aux.
output
*
Opto aux.
input
†
TTL/LVDS aux. input
‡
TTL/LVDS aux. output
‡
M_AUX_IOn n
1111121212120000 234567891011101110111011
for M_DEVm
**
m
012301230123
0/1/
2/3
0/1/
2/3
0/1/
2/3
0/1/
2/3
0/1/
2/3
0/1/
2/3
0/1/
2/3
0/1/
2/3
00112233
Functionality
Acquisition path P0_TTL_AUX(TRIG)_IN P1_TTL_AUX(TRIG)_IN P2_TTL_AUX(TRIG)_IN P3_TTL_AUX(TRIG)_IN P0_TTL_AUX(EXP)_OUT P1_TTL_AUX(EXP)_OUT P2_TTL_AUX(EXP)_OUT P3_TTL_AUX(EXP)_OUT P0_OPTO_AUX(TRIG)_IN P1_OPTO_AUX(TRIG)_IN P2_OPTO_AUX(TRIG)_IN P3_OPTO_AUX(TRIG)_IN LVDS/TTL_AUX_IN0 LVDS/TTL_AUX_IN1 LVDS/TTL_AUX_IN2 LVDS/TTL_AUX_IN3 LVDS/TTL_AUX_IN4 LVDS/TTL_AUX_IN5 LVDS/TTL_AUX_IN6 LVDS/TTL_AUX_IN7 P0_LVDS/TTL_AUX_OUT0 P0_LVDS/TTL_AUX_OUT1 P1_LVDS/TTL_AUX_OUT0 P1_LVDS/TTL_AUX_OUT1 P2_LVDS/TTL_AUX_OUT0 P2_LVDS/TTL_AUX_OUT1 P3_LVDS/TTL_AUX_OUT0 P3_LVDS/TTL_AUX_OUT1
Timer
(M_TIMERn
**
)
01 12
11 12
21 12
31 12