Specifications

Matrox Solios eCL/XCL acquisition section 61
Type of signal
Acquisition path Max # signals
*
LVDS cam. ctrl Received with data LVDS dedicated signals
† ‡
CL connect. 0 CL connect. 1
CL connect. 0 CL connect. 1
CC1 CC2 CC3 CC4 CC1 CC2 CC3 CC4
Frame valid input 01 0
11 0
VSYNC output 010000 P0_LVDS_VSYNC_OUT
1 1 0000 P1_LVDS_VSYNC_OUT
Line valid input 01 0
11 0
HSYNC output 010000 P0_LVDS_HSYNC_OUT
1 1 0000 P1_LVDS_HSYNC_OUT
Data valid input 01 0
11 0
Clock input 01 Xclk (CL connect. 0)
11 Xclk (CL connect. 1)
Clock output 010000 P0_LVDS_CLK_OUT
1 1 0000 P1_LVDS_CLK_OUT
*. The maximum # for each signal type cannot always be attained. The actual maximum depends on whether the required auxiliary signals are
available or have been defined as another type.
†. In this column, each signal is a dedicated signal (that is, it cannot be redefined as another type of signal).
‡. Clock input is received on the Camera Link connectors, whereas the other signals in this column are received on/transmitted from external aux-
iliary I/O connector 0 (DBHD-44).