Specifications

138 Appendix B: Technical information
8+,24- LVDS/TTL_AUX_IN2 M_AUX_IO4 M_DEV0/
M_DEV1/
M_DEV2/
M_DEV3
LVDS or TTL auxiliary signal (input), shared between all
acquisition paths for trigger input (trigger controller 2 on
acq path 0; 2 on acq path 1; 2 on acq path 2; 2 on acq
path 3) or user input, and dedicated to acquisition path 1
for field polarity, data valid, CSYNC, or HSYNC input.
9 GND N/A N/A Ground.
10 GND N/A N/A Ground.
11+,27- P1_LVDS/TTL_AUX_OUT1 M_AUX_IO11 M_DEV1 LVDS or TTL auxiliary signal (output) for acquisition path
1, which supports: user output (M_USER_BIT1), timer
output (M_TIMER2 on M_DEV1), or VSYNC output.
12+,28- LVDS/TTL_AUX_IN1 M_AUX_IO3 M_DEV0/
M_DEV1/
M_DEV2/
M_DEV3
LVDS or TTL auxiliary signal (input), shared between all
acquisition paths for trigger input (trigger controller 3 on
acq path 0; 3 on acq path 1; 3 on acq path 2; 3 on acq
path 3) or user input, and dedicated to acquisition path 0
for timer clock or VSYNC input.
13 GND N/A N/A Ground.
14 GND N/A N/A Ground.
15+,30- P0_LVDS/TTL_AUX_OUT0 M_AUX_IO10 M_DEV0 LVDS or TTL auxiliary signal (output) for acquisition path
0, which supports: user output (M_USER_BIT0), timer
output (M_TIMER1 on M_DEV0), or HSYNC output.
19 GND N/A N/A Ground.
20+,4- P2_LVDS/TTL_AUX_OUT1 M_AUX_IO11 M_DEV2 LVDS or TTL auxiliary signal (output) for acquisition path
2, which supports: user output (M_USER_BIT1), timer
output (M_TIMER2 on M_DEV2), or VSYNC output.
21 GND N/A N/A Ground.
23 GND N/A N/A Ground.
26 GND N/A N/A Ground.
32+,31- LVDS/TTL_AUX_IN6 M_AUX_IO8 M_DEV0/
M_DEV1/
M_DEV2/
M_DEV3
LVDS or TTL auxiliary signal (input), shared between all
acquisition paths for trigger input (trigger controller 2 on
acq path 0; 2 on acq path 1; 2 on acq path 2; 2 on acq
path 3) or user input, and dedicated to acquisition path 3
for field polarity, data valid, CSYNC, or HSYNC input.
33+,18- P3_LVDS/TTL_AUX_OUT0 M_AUX_IO10 M_DEV3 LVDS or TTL auxiliary signal (output) for acquisition path
3, which supports: user output (M_USER_BIT0), timer
output (M_TIMER1 on M_DEV3), or HSYNC output.
35+,34- LVDS/TTL_AUX_IN0 M_AUX_IO2 M_DEV0/
M_DEV1/
M_DEV2/
M_DEV3
LVDS or TTL auxiliary signal (input), shared between all
acquisition paths for trigger input (trigger controller 2 on
acq path 0; 2 on acq path 1; 2 on acq path 2; 2 on acq
path 3) or user input, and dedicated to acquisition path 0
for field polarity, data valid, CSYNC, or HSYNC input.
Pin
Hardware signal name
*
MIL constant for
auxiliary signal
†
Digitizer device
number for
auxiliary signal
Description