Specifications

Connectors on Matrox Solios eA/XA 137
In addition, all the signals can be either LVDS or TTL; when TTL, they are
expected on the pin denoted as positive.
The pinout for this connector is as follows. The description of each auxiliary signal
states whether the signal is specific to an acquisition path and the type of signals
that can be routed onto it.
1
16
31
15
30
44
Pin
Hardware signal name
*
MIL constant for
auxiliary signal
†
Digitizer device
number for
auxiliary signal
Description
1+,16- LVDS/TTL_AUX_IN7 M_AUX_IO9 M_DEV0/
M_DEV1/
M_DEV2/
M_DEV3
LVDS or TTL auxiliary signal (input), shared between all
acquisition paths for trigger input (trigger controller 3 on
acq path 0; 3 on acq path 1; 3 on acq path 2; 3 on acq
path 3) or user input, and dedicated to acquisition path 3
for field polarity, data valid, CSYNC, or HSYNC input.
2+,17- P3_LVDS/TTL_AUX_OUT1 M_AUX_IO11 M_DEV3 LVDS or TTL auxiliary signal (output) for acquisition path
3, which supports: user output (M_USER_BIT1), timer
output (M_TIMER2 on M_DEV3), or VSYNC output.
3 GND N/A N/A Ground.
6+,5- LVDS/TTL_AUX_IN5 M_AUX_IO7 M_DEV0/
M_DEV1/
M_DEV2/
M_DEV3
LVDS or TTL auxiliary signal (input), shared between all
acquisition paths for trigger input (trigger controller 3 on
acq path 0; 3 on acq path 1; 3 on acq path 2; 3 on acq
path 3) or user input, and dedicated to acquisition path 2
for field polarity, data valid, CSYNC, or HSYNC input.
7+,22- LVDS/TTL_AUX_IN4 M_AUX_IO6 M_DEV0/
M_DEV1/
M_DEV2/
M_DEV3
LVDS or TTL auxiliary signal (input), shared between all
acquisition paths for trigger input (trigger controller 2 on
acq path 0; 2 on acq path 1; 2 on acq path 2; 2 on acq
path 3) or user input, and dedicated to acquisition path 2
for field polarity, data valid, CSYNC, or HSYNC input.