Specifications
Connectors on Matrox Solios eCL/XCL dual-Base/single-Medium and eCL/XCL-F boards 129
A6 P0_TTL_AUX_IO_0 M_AUX_IO8 M_DEV0 TTL auxiliary signal (input/output) for acquisition path 0, which
supports: timer output (M_TIMER3 on M_DEV0), trigger input
(trigger controller 0 on acq path 0), user input, user output
(M_USER_BIT2), or field polarity input.
A7 P0_TTL_AUX_IO_1 M_AUX_IO9 M_DEV0 TTL auxiliary signal (input/output) for acquisition path 0, which
supports: timer output (M_TIMER1/M_TIMER4 on M_DEV0),
trigger input (trigger controller 1 on acq path 0), user input, or
user output (M_USER_BIT3).
A8 P1_TTL_AUX_IO_0 M_AUX_IO8 M_DEV1 TTL auxiliary signal (input/output) for acquisition path 1, which
supports: timer output (M_TIMER3 on M_DEV1), trigger input
(trigger controller 0 on acq path 1), user input, user output
(M_USER_BIT2), or field polarity input.
A9 GND Ground.
A10, B9 P0_LVDS_AUX_IN0 M_AUX_IO10 M_DEV0 LVDS auxiliary signal (input) for acquisition path 0, which sup-
ports: trigger input (trigger controller 0 on acq path 0), user
input, field polarity input, or quadrature input bit 0.
A11, B10 P0_LVDS_AUX_IN1 M_AUX_IO11 M_DEV0 LVDS auxiliary signal (input) for acquisition path 0, which sup-
ports: trigger input (trigger controller 1 on acq path 0), user
input, timer clock input, or quadrature input bit 1.
A12, B11 LVDS_AUX_IN0 M_AUX_IO4 M_DEV0/
M_DEV1
LVDS auxiliary signal (input), shared between both acquisition
paths for trigger input (trigger controller 2 on acq path 0; 2 or 0
on acq path 1) or user input, and dedicated to acquisition path 1
for field polarity input or quadrature input bit 0.
A13, B13 LVDS_AUX_IN1 M_AUX_IO5 M_DEV0/
M_DEV1
LVDS auxiliary signal (input), shared between both acquisition
paths for trigger input (trigger controller 3 on acq path 0; 3 or 1
on acq path 1) or user input, and dedicated to acquisition path 1
for timer clock input or quadrature input bit 1.
A14, B14 P0_LVDS_AUX_OUT0 M_AUX_IO12 M_DEV0 LVDS auxiliary signal (output) for acquisition path 0, which sup-
ports: timer output (M_TIMER1 on M_DEV0) or user output
(M_USER_BIT0).
A15, B15 P0_LVDS_AUX_OUT1 M_AUX_IO13 M_DEV0 LVDS auxiliary signal (output) for acquisition path 0, which sup-
ports: timer output (M_TIMER2 on M_DEV0) or user output
(M_USER_BIT1).
A16, B16 P1_LVDS_AUX_OUT0 M_AUX_IO12 M_DEV1 LVDS auxiliary signal (output) for acquisition path 1, which sup-
ports: timer output (M_TIMER1 on M_DEV1) or user output
(M_USER_BIT0).
A17, B17 P1_LVDS_AUX_OUT1 M_AUX_IO13 M_DEV1 LVDS auxiliary signal (output) for acquisition path 1, which sup-
ports: timer output (M_TIMER2 on M_DEV1) or user output
(M_USER_BIT1).
Pin Hardware signal name MIL constant for
auxiliary signal
*
Digitizer
device
number for
auxiliary
signal
Description