Specifications

Connectors on Matrox Solios eCL/XCL dual-Base/single-Medium and eCL/XCL-F boards 125
12+,28- LVDS_AUX_IN1 M_AUX_IO5 M_DEV0/
M_DEV1
LVDS auxiliary signal (input), shared between both
acquisition paths for trigger input (trigger controller 3 on
acq path 0; 3 or 1 on acq path 1) or user input, and
dedicated to acquisition path 1 for timer clock input or
quadrature input bit 1.
13 P0_TTL_AUX_IO_1 M_AUX_IO9 M_DEV0 TTL auxiliary signal (input/output) for acquisition path 0,
which supports: timer output (M_TIMER1/M_TIMER4 on
M_DEV0), trigger input (trigger controller 1 on acq path 0),
user input, or user output (M_USER_BIT3).
14 GND N/A N/A Ground.
15 TTL_AUX_IO_1 M_AUX_IO3 M_DEV0/
M_DEV1
TTL auxiliary signal (input/output), shared between both
acquisition paths for trigger input (trigger controller 3 on
acq path 0; 3 on acq path 1), user input, or user output
(M_USER_BIT5), and dedicated to acquisition path 1 for
timer output (M_TIMER2 on M_DEV1).
16 GND N/A N/A Ground.
19+,3- P0_LVDS_AUX_OUT1 M_AUX_IO13 M_DEV0 LVDS auxiliary signal (output) for acquisition path 0, which
supports: timer output (M_TIMER2 on M_DEV0) or user
output (M_USER_BIT1).
20+,4- P0_LVDS_AUX_OUT0 M_AUX_IO12 M_DEV0 LVDS auxiliary signal (output) for acquisition path 0, which
supports: timer output (M_TIMER1 on M_DEV0) or user
output (M_USER_BIT0).
24+,8- OPTO_AUX_IN0 M_AUX_IO0 M_DEV0/
M_DEV1
Opto-isolated auxiliary signal (input), shared between both
acquisition paths for trigger input (trigger controller 2 on
acq path 0; 2 or 0 on acq path 1) or user input, and
dedicated to acquisition path 1 for field polarity input.
29 GND N/A N/A Ground.
30 GND N/A N/A Ground.
32+,31- LVDS_AUX_IN0 M_AUX_IO4 M_DEV0/
M_DEV1
LVDS auxiliary signal (input), shared between both
acquisition paths for trigger input (trigger controller 2 on
acq path 0; 2 or 0 on acq path 1) or user input, and
dedicated to acquisition path 1 for field polarity input or
quadrature input bit 0.
33+,18- P1_LVDS_AUX_OUT0 M_AUX_IO12 M_DEV1 LVDS auxiliary signal (output) for acquisition path 1, which
supports: timer output (M_TIMER1 on M_DEV1) or user
output (M_USER_BIT0).
34 GND N/A N/A Ground.
35 P1_TTL_AUX_IO_0 M_AUX_IO8 M_DEV1 TTL auxiliary signal (input/output) for acquisition path 1,
which supports: timer output (M_TIMER3 on M_DEV1),
trigger input (trigger controller 0 on acq path 1), user input,
user output (M_USER_BIT2), or field polarity input.
Pin Hardware signal name MIL constant for
auxiliary signal
*
Digitizer
device number
for auxiliary
signal
Description