Specifications

106 Appendix B: Technical information
• 64/128/256 Mbytes of 83 MHz DDR SDRAM used as acquisition memory.
1.32 Gbytes/sec of memory bandwidth. Note that when the optional Processing
FPGA is installed, these numbers increase to 100 MHz and 1.6 Gbytes/sec
respectively.
• Eight TTL/LVDS auxiliary input signals (trigger input, field polarity input, data
valid input, timer-clock input, synchronization input, or user input). See the
Matrox Solios hardware reference chapter for supported configurations.
• Supports a 64-bit 66/100/133 MHz 3.3 V PCI-X (or a 32/64-bit 33/66 MHz
3.3 V or 5 V conventional PCI) Host interface for Matrox Solios XA, a x4 or
greater PCIe Host interface for Matrox Solios eA, and a x1 or greater Host interface
for Matrox Solios eA Single.
Optional features for Matrox Solios boards
• Processing FPGA
*
. The Processing FPGA can be either the Altera Stratix I EP1S30
or the Altera Stratix I EP1S40. These have 32,470 and 41,250 logic elements,
respectively. The Processing FPGA can come with either 4 or 8 Mbytes of QDRII
SRAM. It can also come with 64, 128, or 256 Mbytes of DDR SDRAM.
*. The Processing FPGA option is not available for Matrox Solios eCL/XCL-B,
eA/XA Single, nor the 66 MHz version of the Matrox Solios eCL/XCL dual-Base/sin-
gle-Medium.