Specifications

Board summary 103
• Instead of being mapped through a LUT, 14- and 16-bit data by-pass the LUTs.
• For Matrox Solios eCL/XCL dual-Base/single-Medium in single-Medium mode,
64/128/256 Mbytes of 83 MHz DDR SDRAM used as acquisition memory, with
1.32 Gbytes/sec of memory bandwidth is available. Note that when the optional
Processing FPGA is installed or when the fast Camera Link board is used, these
numbers increase to 100 MHz and 1.6 Gbytes/sec, respectively. For Matrox Solios
eCL/XCL-F, 64/128/256 Mbytes of 110 MHz DDR SDRAM is available with
1.76 Gbytes of memory bandwidth.
• Six TTL auxiliary I/O signals (trigger input, field polarity input, user input, user
output, or timer output). See the Matrox Solios hardware reference chapter for
supported configurations.
• Four LVDS auxiliary input signals (trigger input, field polarity input, timer-clock
input, quadrature input, or user input). See the Matrox Solios hardware reference
chapter for supported configurations.
• Four LVDS auxiliary output signals (timer output or user output). See the Matrox
Solios hardware reference chapter for supported configurations.
• Separate LVDS pixel clock outputs, HSYNC outputs, and VSYNC outputs.
• Four opto-isolated auxiliary input signals (trigger input, field polarity input, or
user input). See the Matrox Solios hardware reference chapter for supported
configurations.
• One LVDS serial port.