Specifications

Board summary 101
• Two LVDS auxiliary input signals (trigger input, field polarity input, timer-clock
input, quadrature input, or user input). See the Matrox Solios hardware reference
chapter for supported configurations.
• Two opto-isolated auxiliary input signals (trigger input, field polarity input, or
user input). See the Matrox Solios hardware reference chapter for supported
configurations.
• One LVDS serial port.
Features specific to Matrox Solios eCL/XCL dual-Base/single-Medium in
dual-Base mode
• Supports two independent video sources in the Camera Link Base configuration.
• Available in two maximum Camera Link frequencies. Standard Camera Link
boards have a maximum frequency of 66 MHz; while fast Camera Link boards
support a maximum frequency of 85 MHz.
• In dual-Base mode, the programmable LUTs can be operated in the following
configurations per acquisition path
*
:
- 8 palettes of one, two, three, or four 256-entry 8-bit LUTs.
- 4 palettes of one or two 1024-entry 8- or 16-bit LUTs.
- 1 palette of one or two 4096-entry 8- or 16-bit LUTs.
• Instead of being mapped through a LUT, 14- and 16-bit data by-pass the LUTs.
• 64/128/256 Mbytes of 83 MHz DDR SDRAM used as acquisition memory.
1.32 Gbytes/sec of memory bandwidth. Note that when the optional Processing
FPGA is installed or when the fast Camera Link board is used, these numbers
increase to 100 MHz and 1.6 Gbytes/sec, respectively.
• Two separate LVDS pixel clock outputs, HSYNC outputs, and VSYNC outputs.
*. For example, two 1024-entry 8-bit LUTs can map 2-tap 10-bit data to 8-bit values. In
addition one 1024-entry 8-bit LUT can map 1-tap 10-bit data to 8-bit values.