Vodafone Chair Mobile Communications Systems, Prof. Dr.-Ing. G.
Introduction chair Hardware Why to use digital signal processing? General introduction to DSPs The TMS320C6711 DSP Architecture Overview Peripherals DSK6711 evaluation board - Software Code Composer Studio DSP/BIOS Multi-channel Buffered Serial Port (McBSP) TU Dresden, 4/29/2008 Slide 2
chair Hardware TU Dresden, 4/29/2008 Slide 3
Digital Signal Processing (DSP) chair Wireless / Cellular Voice-band audio RF codecs Voltage regulation Consumer Audio Stereo A/D, D/A PLL Mixers HDD PRML read channel MR pre-amp Servo control SCSI tranceivers DSP: Technology Enabler Automotive Digital radio A/D/A Active suspension Voltage regulation Multimedia Stereo audio Imaging Graphics palette Voltage regulation TU Dresden, 4/29/2008 DTAD Speech synthesizer Mixed-signal processor Slide 4
System Considerations chair Interfacing Performance Power Size Ease-of Use • Programming • Interfacing • Debugging TU Dresden, 4/29/2008 Cost • Device cost • System cost • Development cost • Time to market Integration • Memory • Peripherals Slide 5
Why Go Digital? chair Digital signal processing techniques are now so powerful that sometimes it is extremely difficult, if not impossible, for analogue signal processing to achieve similar performance.
Why Go Digital? chair Analogue signal processing is achieved by using analogue components such as: Resistors Capacitors Inductors The inherent tolerances associated with these components, temperature, voltage changes and mechanical vibrations can dramatically affect the effectiveness of the analogue circuitry TU Dresden, 4/29/2008 Slide 7
Why Go Digital? chair With DSP? - It is easy to: Change applications Correct applications Update applications Additionally DSPs reduce: Noise susceptibility Chip count Development time Cost Power consumption TU Dresden, 4/29/2008 Slide 8
chair General Introduction to DSPs TU Dresden, 4/29/2008 Slide 9
What Problem Are We Trying To Solve? chair x ADC Digital sampling of an analog signal: DSP Y DAC Most DSP algorithms can be expressed as: count A Y = t TU Dresden, 4/29/2008 Σ i = 1 ai * xi for (i = 1; i < count; i++){ sum += m[i] * n[i]; } Slide 10
What are the typical DSP algorithms? chair The Sum of Products (SOP) is the key element in most DSP algorithms: Algorithm Equation M Finite Impulse Response Filter y ( n ) = ∑ ak x ( n − k ) k =0 M Infinite Impulse Response Filter y ( n) = ∑ N a k x ( n − k )+ k =0 ∑b k y (n − k ) k =1 N Convolution y ( n) = ∑ x ( k ) h( n − k ) k =0 N −1 Discrete Fourier Transform Discrete Cosine Transform TU Dresden, 4/29/2008 X (k ) = ∑ x(n) exp[− j (2π / N )nk ] n =0 F (u ) = N −1 ⎡ π ⎤ ∑ c
Why do we need DSP processors? chair Use a DSP processor when the following are required: Cost saving Smaller size Low power consumption Processing of many “high” frequency signals in real-time Use a GPP processor when the following are required: Large memory Advanced operating systems TU Dresden, 4/29/2008 Slide 12
Hardware vs. Microcode multiplication chair DSP processors are optimized to perform multiplication and addition operations. Multiplication and addition are done in hardware and in one cycle. Example: 4-bit multiply (unsigned). Hardware Microcode 1011 x 1110 10011010 1011 x 1110 0000 1011. 1011.. 1011...
General Purpose DSP vs. DSP in ASIC chair Application Specific Integrated Circuits (ASICs) are semiconductors designed for dedicated functions.
Floating vs.
chair TMS320C6711 Architectural Overview TU Dresden, 4/29/2008 Slide 16
General DSP System Block Diagram chair Internal Memory Internal Buses External Memory Central Processing Unit TU Dresden, 4/29/2008 P E R I P H E R A L S Slide 17
‘6711 CPU Overview chair Specification Clock Rate: 100/150 MHz Î 600/900 MFLOPS 0.
‘6711 CPU Overview chair VelociTI Î advanced very-long instruction words (VLIW) Program Memory Width is 256 Bit Up to 8 32-Bit instructions can be executed in parallel/Cycle 16, 32 and 40 bit fixed point operands 32 and 64 bit floating point operands Instruction parallelism is detected at compile-time no data dependency checking is done in Hardware.
Functional Block and CPU Diagram chair TU Dresden, 4/29/2008 Slide 20
A ‘6711 Datapath chair .S & .L Arithmetic, Logical & Branch functions .M Multiply, Rotation, Bit expansion .
Functional Units and Operations Performed chair TU Dresden, 4/29/2008 Slide 22
C6700: Instruction Set chair .S Unit .S .S .L .L .D .D .M .M TU Dresden, 4/29/2008 ADD ADDK ADD2 AND B CLR EXT MV MVC MVK MVKH NEG NOT OR SET SHL SHR SSHL SUB SUB2 XOR ZERO ABSSP ABSDP CMPGTSP CMPEQSP CMPLTSP CMPGTDP CMPEQDP CMPLTDP RCPSP RCPDP RSQRSP RSQRDP SPDP .D Unit ADD NEG ADDAB (B/H/W) STB (B/H/W) LDB (B/H/W) SUB LDDW SUBAB (B/H/W) MV ZERO .
'C6x System Block Diagram chair Program RAM Data Ram Addr Internal Buses DMA D (32) EMIF .M1 .M2 .L1 .L2 .S1 .S2 Control Regs Serial Port Regs (B0-B15) - Sync - Async Regs (A0-A15) Ext’l Memory .D1 .
‘C6000 Internal Buses chair Internal Program Addr x32 Program Data x256 Data Addr - T1 x32 Data Data - T1 x32/64 Data Addr - T2 x32 Data Data - T2 x32/64 PC Memory External Memory Peripherals TU Dresden, 4/29/2008 DMA Addr - Read x32 DMA Data - Read x32 DMA Addr - Write x32 DMA Data - Write x32 A regs B regs DMA Slide 25
How are Peripherals Controlled? chair Control and configuration of internal peripherals is done by memory mapped control registers There is a separate memory mapped register file of control registers Example of Timer mode control register: 31 12 Rsvd 11 TSAT 7 6 5 4 3 HLD GO Rsvd PWID DATIN TU Dresden, 4/29/2008 10 9 INVIMP CLKSRC 2 1 DATOUT INVOUT 8 C/P 0 Func Slide 26
‘C6711 Memory Map 0000_0000 64K x 8 Internal External Memory (L2 cache) Byte Address 0180_0000 chair Async (SRAM, ROM, etc.
Memory Map chair 0000_0000 64KB Internal 16MB SDRAM (Progam or Data) 0180_0000 On-chip Periph 128K byte FLASH 4 byte I/O Port 8000_0000 9000_0000 A000_0000 B000_0000 9008_0000 LED’s Switches DSK status DSK rev# Daughter Card 256MB External 256MB External 256MB External 256MB External Available via Daughter Card Connector FFFF_FFFF TU Dresden, 4/29/2008 Slide 28
Operands chair Operands can be 5-bit constants (or 16-bit in some special instruct.) 32-bit Registers 40-bit Registers 64-bit Registers A 40-bit or a 64-bit register can be obtained by concatenating two registers The registers must be from the same side The first register must be even and the second odd (e.g.
Conditional execution chair All instructions in each Functional Unit of both Data paths can be executed conditionally Only the Registers A1, A2, B0, B1, B2 can hold the condition Conditional Execution uses the Syntax [!condition] Instruction e.g [!B0] [B0] TU Dresden, 4/29/2008 ADD.L1 ADD.
Branches chair Branches are required to realize loops and change the program flow Branches are very useful in conjunction with conditional execution There are two branch types supported: Relative Branching Absolute Branching TU Dresden, 4/29/2008 Slide 31
More on the Branch Instruction (1) chair With this processor all the instructions are encoded in a 32-bit. Therefore the label must have a dynamic range of less than 32-bit as the instruction B has to be coded. 32-bit B Case 1: 21-bit relative address B .S1 label Relative branch. Label limited to +/- 220 offset.
More on the Branch Instruction (2) chair By specifying a register as an operand instead of a label, it is possible to have an absolute branch. This will allow a dynamic range of 232. 32-bit B Case 2: B .S2 5-bit register code register Absolute branch. Operates on .
Getting Data from the Memory chair All Instructions work exclusively on Registers The .
Addressing Modes chair There are two addressing modes supported: Linear Addressing Circular Addressing (e.g. Convolution) Circular Addressing supports block sizes 2N Only the lower N bits of the Address are modified by address arithmetic. This equals mod(2N) operations.
Floating vs. Fixed point processors chair Fixed point arithmetic 16-bit (integer or fractional) Signed or unsigned Floating point arithmetic 32-bit single precision 64-bit single precision Using signed and unsigned integers: N −1 ∑ y (n ) = a(k )x(n − k ) Multiplication overflow. k =0 Addition overflow Î Saturate the result Î Double precision result Î Fractional arithmetic e.g.
C6000 C Data Types chair Type Size Representation char, signed char unsigned char short unsigned short int, signed int unsigned int long, signed long unsigned long enum float double long double pointers 8 bits 8 bits 16 bits 16 bits 32 bits 32 bits 40 bits 40 bits 32 bits 32 bits 64 bits 64 bits 32 bits ASCII ASCII 2’s complement binary 2s complement binary 2’s complement binary 2’s complement IEEE 32-bit IEEE 64-bit IEEE 64-bit binary TU Dresden, 4/29/2008 Slide 37
Numerical Issues - Useful Tips chair Multiply by 2: Use shift left Divide by 2: Use shift right Log2N: Use shift Sine, Cosine, Log: Use look up tables To convert a fractional number to hex: Num x 215 Then convert to hex e.g: convert 0.5 to hex TU Dresden, 4/29/2008 0.
Numerical Issues - 32-bit Multiplication chair It is possible to perform 32-bit multiplication using 16-bit multipliers. Example: c = a x b (with 32-bit values).
chair Selected ‘6711 Peripherals TU Dresden, 4/29/2008 Slide 40
C6000 Peripherals chair XB Host Port PCI Host μC External Memory 16/32 EMIF Timer/Count .D1 .D2 .M1 .M2 .L1 .L2 .S1 .
The McBSP chair Multichannel Buffered Serial Port Up to 100 Mb/sec performance 2 (or 3) full-duplex, synchronous serial-ports Enables direct interfacing to industry standard Codecs, Analog interface Chips and other serially connected devices Supports a wide range of data-sizes, including 8, 12, 16, 20, 24 and 32 bits ÎBit, Word(channel), Frame, Phase ÎIn our lab the McBSP is used to connect to the A/D, D/A daughter card TU Dresden, 4/29/2008 Slide 42
PCM3003 chair MONOLITHIC 20-BIT DS ADC AND DAC 16-/20-BIT INPUT/OUTPUT DATA HARDWARE CONTROL: PCM3003 STEREO ADC: SNR: 90dB & DynamicRange: 90dB STEREO DAC: SNR: 94dB & Dynamic Range: 94dB Digital Attenuation (256 Steps), Soft Mute, Digital Loop Back SAMPLING RATE: Up to 48kHz SYSTEM CLOCK: 256fS, 384fS, 512fS TU Dresden, 4/29/2008 Slide 43
What is the bootloader? VCC chair VCC Boot Config DMA L2 Cache EPROM EMIF L1P Cache Addr 0000 0001 0002 0003 ... CPU L1D Cache C6211/C6711 When the DSP is NOT powered or under reset the internal program memory is in a random state.
What is the bootloader? VCC chair VCC Boot Config DMA L2 Cache EPROM EMIF L1P Cache Addr 0000 0001 0002 0003 ... CPU PC=0003 PC=0000 PC=0001 PC=0002 L1D Cache C6211/C6711 When the DSP is powered and the CPU is taken out of reset the internal memory is still in a random state and the program will start running for address zero.
What is the bootloader? VCC chair VCC Boot Config DMA L2 Cache EPROM EMIF L1P Cache CPU L1D Cache C6211/C6711 With the boot, a portion of code can be automatically copied from external to internal memory.
Interrupts chair DSPs must be able to execute tasks on asynchronous events Interrupts suspend the current processor task and save its context A interrupt service routine (ISR) is executed After completion of the ISR, the context of the former task is restored and the execution continues Interrupts are organized hierarchically Î vs.
Interrupt Interrupt- and Thread Types chair HWI priorities set by hardware ÎOne ISR per interrupt 14 SWI priority levels ÎMultiple SWIs at each level 15 TSK priority levels ÎMultiple TSKs at each level Multiple IDL functions ÎContinuous loop ÎHWI triggered by hardware interrupt ÎIDL runs as the background thread TU Dresden, 4/29/2008 Slide 48
chair The DSK6711 Development Kit TU Dresden, 4/29/2008 Slide 49
DSK Contents chair Hardware 150 MHz ‘C6711 DSP TI 16-bit A/D Converter (‘AD535) External Memory 16M Bytes SDRAM 128K Bytes Flash ROM LED’s Daughter card expansion Power Supply & Parallel Port Cable Software Code Generation Tools (C Compiler, Assembler & Linker) Code Composer Debugger (256K program limitation) Example Programs & S/W Utilities Power-on Self Test Flash Utility Program Board Confidence Test Host access via DLL Sample Program(s) TU Dresden, 4/29/2008
C6711 DSK Overview chair 1.8V Power Supply 16M SDRAM 128K FLASH Daughter Card I/F (EMIF Connector) Parallel Port I/F TMS320C6711 Power Jack ‘C6711 DSP D. Card I/F (Periph Con.) Power LED User DIP switches 3.
Software: (4) PC Æ DSK Communications chair CCS uses parallel port to control DSP via JTAG port You can use full TI eXtended Dev System (XDS) via 14 pin header connector Communicate from Windows program (C++, VB) via parallel port using Win32 DLL Use HPI via Win32 DLL DSP JTAG ....... .......
What happens to the Source-Code? chair TU Dresden, 4/29/2008 Slide 53
