6.7

The first layer of page tables stores guest virtual-to-physical translations, while the second layer of page
tables stores guest physical-to-machine translation. The TLB (translation look-aside buffer) is a cache of
translations maintained by the processor's memory management unit (MMU) hardware. A TLB miss is a
miss in this cache and the hardware needs to go to memory (possibly many times) to find the required
translation. For a TLB miss to a certain guest virtual address, the hardware looks at both page tables to
translate guest virtual address to machine address. The first layer of page tables is maintained by the
guest operating system. The VMM only maintains the second layer of page tables.
Performance Considerations
When you use hardware assistance, you eliminate the overhead for software memory virtualization. In
particular, hardware assistance eliminates the overhead required to keep shadow page tables in
synchronization with guest page tables. However, the TLB miss latency when using hardware assistance
is significantly higher. By default the hypervisor uses large pages in hardware assisted modes to reduce
the cost of TLB misses. As a result, whether or not a workload benefits by using hardware assistance
primarily depends on the overhead the memory virtualization causes when using software memory
virtualization. If a workload involves a small amount of page table activity (such as process creation,
mapping the memory, or context switches), software virtualization does not cause significant overhead.
Conversely, workloads with a large amount of page table activity are likely to benefit from hardware
assistance.
By default the hypervisor uses large pages in hardware assisted modes to reduce the cost of TLB misses.
The best performance is achieved by using large pages in both guest virtual to guest physical and guest
physical to machine address translations.
The option LPage.LPageAlwaysTryForNPT can change the policy for using large pages in guest physical
to machine address translations. For more information, see Advanced Memory Attributes.
Support for Large Page Sizes
ESXi provides limited support for large page sizes.
x86 architecture allows system software to use 4KB, 2MB and 1GB pages. We refer to 4KB pages as
small pages while 2MB and 1GB pages are referred to as large pages. Large pages relieve translation
lookaside buffer (TLB) pressure and reduce the cost of page table walks, which results in improved
workload performance.
In virtualized environments, large pages can be used by the hypervisor and the guest operating system
independently. While the biggest performance impact is achieved if large pages are used by the guest
and the hypervisor, in most cases a performance impact can be observed even if large pages are used
only at the hypervisor level.
ESXi hypervisor uses 2MB pages for backing guest vRAM by default. vSphere 6.7 ESXi provides a
limited support for backing guest vRAM with 1GB pages. For more information, see Backing Guest vRAM
with 1GB Pages.
vSphere Resource Management
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