6.5.1

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The dashed arrows show the mapping from guest virtual memory to machine memory in the shadow
page tables also maintained by the VMM. The underlying processor running the virtual machine uses
the shadow page table mappings.
Software-Based Memory Virtualization
ESXi virtualizes guest physical memory by adding an extra level of address translation.
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The VMM maintains the combined virtual-to-machine page mappings in the shadow page tables. The
shadow page tables are kept up to date with the guest operating system's virtual-to-physical mappings
and physical-to-machine mappings maintained by the VMM.
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The VMM intercepts virtual machine instructions that manipulate guest operating system memory
management structures so that the actual memory management unit (MMU) on the processor is not
updated directly by the virtual machine.
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The shadow page tables are used directly by the processor's paging hardware.
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There is non-trivial computation overhead for maintaining the coherency of the shadow page tables.
The overhead is more pronounced when the number of virtual CPUs increases.
This approach to address translation allows normal memory accesses in the virtual machine to execute
without adding address translation overhead, after the shadow page tables are set up. Because the
translation look-aside buer (TLB) on the processor caches direct virtual-to-machine mappings read from
the shadow page tables, no additional overhead is added by the VMM to access the memory. Note that
software MMU has a higher overhead memory requirement than hardware MMU. Hence, in order to
support software MMU, the maximum overhead supported for virtual machines in the VMkernel needs to
be increased. In some cases, software memory virtualization may have some performance benet over
hardware-assisted approach if the workload induces a huge amount of TLB misses.
Performance Considerations
The use of two sets of page tables has these performance implications.
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No overhead is incurred for regular guest memory accesses.
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Additional time is required to map memory within a virtual machine, which happens when:
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The virtual machine operating system is seing up or updating virtual address to physical address
mappings.
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The virtual machine operating system is switching from one address space to another (context
switch).
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Like CPU virtualization, memory virtualization overhead depends on workload.
Hardware-Assisted Memory Virtualization
Some CPUs, such as AMD SVM-V and the Intel Xeon 5500 series, provide hardware support for memory
virtualization by using two layers of page tables.
The rst layer of page tables stores guest virtual-to-physical translations, while the second layer of page
tables stores guest physical-to-machine translation. The TLB (translation look-aside buer) is a cache of
translations maintained by the processor's memory management unit (MMU) hardware. A TLB miss is a
miss in this cache and the hardware needs to go to memory (possibly many times) to nd the required
translation. For a TLB miss to a certain guest virtual address, the hardware looks at both page tables to
translate guest virtual address to machine address. The rst layer of page tables is maintained by the guest
operating system. The VMM only maintains the second layer of page tables.
vSphere Resource Management
30 VMware, Inc.