Service Manual Model #: VIZIO P50HDM V, Inc 320A Kalmus Drive Costa Mesa, CA 92626 TEL : +714-668-0588 FAX :+714-668-9099 -TOP Confidential -
Table of Contents CONTENTS PAGE Sections 1. Features 1-1 2. Specifications 2-1 3. On Screen Display 3-1 4. Factory Preset Timings 4-1 5. Pin Assignment 5-1 6. BLOCK DIAGRAM 6-1 7. Main Board I/O Connections 7-1 8. Theory of Circuit Operation 8-1 9. Waveforms 9-1 10. Trouble Shooting 10-1 11. Spare Parts List 11-1 12. Complete Parts List 12-1 Appendix 1. Main Board Circuit Diagram 2. Main Board PCB Layout 3.
VINC Service Manual VIZIO P50HDM COPYRIGHT © 2000 V, INC. ALL RIGHTS RESERVED. IBM and IBM products are registered trademarks of International Business Machines Corporation. Macintosh and Power Macintosh are registered trademarks of Apple Computer, Inc. VINC and VINC products are registered trademarks of V, Inc. VESA, EDID, DPMS and DDC are registered trademarks of Video Electronics Standards Association (VESA). Energy Star is a registered trademark of the US Environmental Protection Agency (EPA).
Chapter 1 Features Wall-mountable New WIDE HD Plasma Panel:1366 x 768 (H x V) TruSurround XT sound system and DCDi by Faroujia video image High definition digital interface – HDMI HDCP supportive Multiple-screen display (picture-on-picture/picture-in-picture) Selectable picture mode 4-language On Screen Display 2 S-video and Composite video inputs 2 Component video inputs 2 HDMI inputs 6 audio stereos, 1 PC Mini-Jack Supporting DVI converted to HDMI Closed caption Gloss front bezel The thinnest model of t
Chapter 2 Specification 1. OPTICAL CHARACTERISTICS Item Specification Display Pixels 1366 (H) x 768 (V) pixels Pixel Pitch 0.810 mm (H) X 0.810mm (V) Pixel Type Non-stripe Color Depth 1,024 (R) x 1,024 (G) x 1,024 (B) colors Active Display Area 1106.5 mm (H) x 622.1 mm(V) Brightness (panel spec) 1000 cd/m2 (Typical) (w/glass filter) Contrast ratio (panel spec) Min.300 cd/m 8000:1 (Typical, dark room) Color Coordinates (typical) White (Panel spec) x=0.300±0.02, y=0.300±0.
Composite Video signal: H: 15.734KHz Component signal: V: 60Hz (NTSC) YPbPr/YCbCr H: 15.734KHz V: 60Hz (NTSC-480i) H: 31KHz V: 60Hz(NTSC-480p) H: 45KHz V: 60Hz(NTSC-720p) H: 33KHz V: 60Hz(NTSC-1080i) 3.
. ENVIRONMENT Operating a. Temperature: 0~40℃ b. c. Relative humidity: 20%~80% RH Altitude: 0~6,560 ft Non-operating a. Temperature: -20~60℃ b. c. Relative humidity: 10%~90% RH Altitude: 0~9,840 ft 8. DIMENSIONS a. Height: 871 mm b. Width: 1241mm c. Depth: 310 mm (with standard), 99 mm (without standard) 9. WEIGHT a. Net: 55.2 +/- 0.5 kgs b. Gross: 65.2 +/- 0.5 kgs CONFIDENTIAL – DO NOT COPY Page 2-3 File No.
Chapter 3 On Screen Display Main unit button POWER MENU ▲ ▼ VOL-/W VOL+/X INPUT OSD Adjustment Mode Image Settings VIDEO Picture Mode(User, Vivid, Movie, Game, Sport) Brightness(0~100) Contrast(0~100) VIDEO Saturation(0~100) VIDEO Hue(-50~50) VIDEO Sharpness(0~24) Advanced VIDEO Noise Reduction VIDEO Motion(0~16) VIDEO Digital(0~64) VIDEO VIDEO Fleshtone Dynamic Off, High, Moderate, Low Contrast (0, 1, 2, 3) PC Auto Adjustment PC Image Position PC Phase PC Clocks / Line PC Co
PC Standard(6500K) PC Cool(9300K) PC User PC Red(0~100) PC Green(0~100) PC Blue(0~100) Display Settings VIDEO Aspect Ratio PC Aspect Ratio Wide, Normal, Zoom, Panoramic* Wide, Normal PIP Off, Large PIP, Small PIP, PIP Mode POP Top-Left, PIP Position Top-Right, Bottom-Left, Bottom-Right PIP Input** Audio Settings Bass(0~20) Treble(0~20) Balance(-10~10) SRS TS XT(Off, On) Auto Volume(On, Off) Speakers(On, Off) Audio Out*** Fixed Volume, Variable Volume Parental Controls VIDEO Pass
VIDEO TV Youth (Unblocked, Blocked) VIDEO TV Youth 7 (Unblocked, Blocked) VIDEO TV G (Unblocked, Blocked) VIDEO TV PG (Unblocked, Blocked) VIDEO TV 14 (Unblocked, Blocked) VIDEO TV MA (Unblocked, Blocked) VIDEO VIDEO Unblocked Movie Rating VIDEO Movie G (Unblocked, Blocked) VIDEO Movie PG (Unblocked, Blocked) VIDEO Movie PG-13 (Unblocked, Blocked) VIDEO Movie R (Unblocked, Blocked) VIDEO Movie NC-17 (Unblocked, Blocked) VIDEO Movie X (Unblocked, Blocked) VIDEO Unblocked Block Unra
VIDEO Change Password VIDEO Please enter new password VIDEO Please re-enter new password VIDEO Clear All (No, Yes) Setup Closed Caption Off, Display CC4, CC1, CC2, TEXT1, CC3, TEXT2, TEXT3, TEXT4 Captions on mute (On, Off) Language English, Français, Español, Italiano Factory Reset (Yes, No) Image Cleaner Firmware Version * HDMI and Component 720P/1080i inputs do not support Panoramic. ** See below for detailed information regarding the PiP sources.
Main \ Sub AV1 AV2 AV2 Analog Analog Digital Digital (S-VIDEO) (S-VIDEO) (VIDEO) (VIDEO) HD1 HD2 HD1 HD2 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x AV1 (S-VIDEO) AV2 (S-VIDEO) AV1 (VIDEO) AV2 (VIDEO) Analog HD1 Analog HD2 Digital HD1 Digital HD2 RGB AV1 x x x x x x x x x x x x x x x x x x x x x x x x x RGB x x Remark： (1)：“x” – Indicates which inputs are available for PIP and POP modes.
Chapter 4 Factory preset timings This timing chart is already preset for this plasma monitor. 1. PC analog preset modes Mode No. Refresh Horizontal Resolution Rate Vertical Frequency Frequency (Hz) (KHz) (Hz) Horizontal Vertical Sync Sync Pixel Rate Polarity Polarity (MHz) (TTL) (TTL) Remark 1 640x480 60 31.5 59.94 N N 25.175 Windows 2 640x480 75 37.5 75.00 N N 31.500 Windows 3 800x600 60 37.9 60.317 P P 40.000 Windows 4 800x600 75 46.9 75 P P 49.
2. HD video digital preset modes at HDMI Mode No. Resolution 1 480i 2 480p 3 720p 4 1080i 3. HD digital preset modes at DVI Through HDMI interface by an optional interface cable 2.3.3.1 video input. 3. 1 Video input Mode No. Resolution 1 480i 2 480p 3 720p 4 1080i 3.2 PC input Mode No. 1 Refresh Horizontal Resolution 640x480 Vertical Rate Frequency Frequency (Hz) (KHz) (Hz) 60 31.5 59.
Chapter 5 Pin Assignment 1.Input There are analog and digital connectors as video input source in this model. 1.1 Analog 1.1.1 RGB Connector a. Type: Analog b. Frequency: H: 30-80KHz c. Signal level: 0.7Vp-p d. Impedance: 75Ω e. Synchronization H/V separate sync: TTL H/V composite sync: Sync on Green TTL f. Video bandwidth: 135MHz g.
1.1.2 RCA-type (Yellow) Composite Video Connector a. Frequency: H: 15.734KHz V: 60Hz b. Signal level: 1Vp-p Sync (H+V): c. Impedance: 75Ω d. Connector type: RCA jack (NTSC) 0.3V below Video (Y+C) 1.1.3 S-Video Connector 4 3 2 1 1, 2 = GND 3 = Luminance (Y) 4 = Chrominance(C) a. Frequency: H: 15.734KHz V: 60Hz (NTSC) b. Signal level: Y: 1Vp-p C: 0.286Vp-p c. Impedance: 75Ω d. Connector type: 4-pin mini DIN 1.1.4 Y-Cb/Pb-Cr/Pr Component video signal a. Frequency: H: 15.
1.1.6 Video audio in a. Signal level: 0.7Vrms b. Impedance: 47KΩ c. Frequency Response: 250Hz-20KHz d. Connector type: RCA L/R: 1.2 Digital - HDMI a. Frequency: H: 15.734KHz V: 60Hz H: 31KHz V: 60Hz H: 45KHz V: 60Hz H: 33KHz V: 60Hz b. Polarity: Positive or Negative c. Type: Type A d. Pin Assignment: Please see below Pin 19 Pin 1 Pin 2 CONFIDENTIAL – DO NOT COPY Page 5-3 File No.
Pin Signal Assignment Pin Signal Assignment 1 TMDS Data2+ 2 TMDS Data2 Shield 3 TMDS Data2- 4 TMDS Data1+ 5 TMDS Data1 Shield 6 TMDS Data1- 7 TMDS Data0+ 8 TMDS Data0 Shield 9 TMDS Data0- 10 TMDS Clock+ 11 TMDS Clock Shield 12 TMDS Clock- 13 CEC 14 Reserved (N.C. on device) 15 SCL 16 SDA 17 DDC/CEC Ground 18 +5V Power 19 Hot Plug Detect 2. Output 2.1 Earphone a. Signal level: 1Vrms (max.) b. Impedance: 32Ω c. Output: 50 mW d.
Chapter 6 Block Diagram System Block Diagram POWER BOARD Y DRIVER BOARD X DRIVER BOARD LVDS BOARD W1 CN12 CN5 CN13 CN3 CN1 MAIN BOARD CN2 J8 J7 IR BOARD EMI Fillter CONFIDENTIAL – DO NOT COPY Page 6-1 File No.
Main board System Block Diagram U26 MAX232A ATXD_HUD J9 2 1 3 J10 2 1 3 ARXD ATXD_HUD VEDIO ATXD ARXD_HUD ARXD_HUD U40 24LC128 EEPROM(8051) UC_SCL/UC_SDA U20 4052 I/O SW U38 SST89C58 HY5DU56822CT-D4 U17 DDR RAM CTZ 51_RXD/51_TXD HY5DU56822CT-D4 U16 DDR RAM HUD FL8532_CTZ Frame Store DDR Interface ADATA[0:23] U42 Sil 9011 HDMI RS W8 51_RXD/51_TXD ARXD ATXD IPCLK0/AHS/AVS/AHREF_DE Frame Store DDR Interface UART 2 Wire Controller HDMI1 AUDIO CN17 BDATA[0:23] U35 Sil 9011 HDMI RS U37 24
Chapter 7 Main Board Internal I/O Connections CN1 CN2 CN3 “DC POWER INPUT’ PIN Description 1 PDP_+5Vsc 2 PDP_+5Vsc 3 PDP_+5Vsc 4 GND 5 GND 6 GND 7 PDP_+12V 8 PDP_+12V 9 GND 10 GND 11 PDP_+12V_FAN 12 PDP_FGND PIN Description 1 PDP_Audio 2 PDP_Audio 3 GND 4 GND “DC POWER INPUT’ “DC POWER INPUT/OUTPUT’ CONFIDENTIAL – DO NOT COPY PIN Description 1 GND 2 VS_ON 3 RLY_ON 4 PDP_+5Vsb Page 7-1 File No.
CN5 CN6 CN7 CONNECTION “KEYPAD” PIN Description 1 LED2_KEYPAD 2 KEY_VCC 3 IR 4 ADC_IN2 5 NC 6 GND 7 +3.3V_LBADC 8 ADC_IN1 9 LED1_KEYPAD_BUF 10 GND P1 GND P2 GND CONNECTION “HDMI/ATSC_UP” PIN Description 1 +5V 2 51_TXD 3 51_RXD 4 GND CONNECTTION “ODC2BI” CONFIDENTIAL – DO NOT COPY PIN Description 1 VGA_SCL_CTZ 2 VGA_SDA_CTZ 3 GND Page 7-2 File No.
CN12 CN13 J7 J8 FAN CONNECTION PIN Description 1 NC 2 FANIN1 3 +12V_FAN 4 FGND PIN Description 1 FANIN1 2 +12V_FAN 3 FGND FAN CONNECTION CONNECTION “SPEAKER R” PIN Description 1 RL- 2 RL+ 3 NC PIN Description 1 LL- 2 LL+ CONNECTION “SPEAKER L” CONFIDENTIAL – DO NOT COPY Page 7-3 File No.
W1 J3 CONNECTION “LVDS” PIN Description PIN Description 1 GND 2 TXA3+ 3 TXA3- 4 TXAC+ 5 TXAC- 6 GND 7 TXA2+ 8 TXA2- 9 TXA1+ 10 TXA1- 11 TXA0+ 12 TXA0- 13 GND 14 GND 15 +5V_SW 16 +5V_SW 17 +5V_SW 18 GND 19 GND 20 NC 21 NC 22 NC 23 NC 24 TXB3+ 25 TXB3- 26 GND 27 VS_ON 28 SCL_33V 29 SDA_33V 30 NC 31 GND SELECT KEY POWER “ON” ADD JUMPER PIN Description Default 1-2 +3.
J9 CONNECTION “PROGRAMUPDATA” “ON” J10 ADD JUMPER PIN Description Default 1-2 ARXD ON 2-3 ARXD_HUD OFF , “OFF” NO JUMPER CONNECTION “PROGRAMUPDATA” “ON” ADD JUMPER PIN Description Default 1-2 ATXD ON 2-3 ATXD_HUD OFF , “OFF” NO JUMPER CONFIDENTIAL – DO NOT COPY Page 7-5 File No.
Chapter 8 Theory of Circuit Operation The operation of User Interface The following diagram provides a brief overview of the user-interactive components of the firmware. Figure 8-1 User Interface Block Diagram The operation of keypad There are 8 keys to control and select the function of SHD-3010 and also have two LED to indicate the status of operation. They are “Power, Source, MENU, ▼▲, + -” keys and LED. 1.
The operation of Video Processor FLI8532 The Genesis Microchip FLI8532 includes an integrated 3-D Digital Video Decoder with Faroudja DCDi CinemaTM video format conversion, video enhancement, and noise reduction. The auto-detection and Faroudja DCDi CinemaTM technology allow the FLI8532 to detect, process, and enhance any video or PC graphic format. The FLI8532 supports many worldwide VBI standards for applications of Teletext, Closed Captioning, V-Chip, and other VBI technologies.
Analog Input Port (AFE): The FLI8532 chip has a sophisticated Analog Front End with 16 reconfigurable inputs through and analog multiplexer to anti-alias filters before the Analog to Digital Converters (ADCs). These integrated features eliminate the need for any devices between the input connector and the pin of the FLI8532.
PORTA also includes optional signals (DIP_EXT_CLAMP, DIP_EXT_COAST, DIP_CLEAN_HS_OUT) for interfacing to external ADC/PLL devices. These signals are not present on PORTB. Bits 7 to 0 of PORTA can be configured as a bidirectional interface for media card applications. Inputs to the digital input port are TTL compatible with a maximum clock speed of 135MHz. Sync and clock polarity is programmable. Due to pin sharing, PORTB is not available when using 48bit double wide TTL output to the panel.
LVDS Transmitter: Two LVDS channels (A and B) are available on the output of the FLI8532 to transmit data and timing information to the display device. The following diagram shows the available LVDS mapping for 30-bit LVDS output which is applying to PDP panel spec: 30-bit LVDS Output Stream To Configure for 30-bit LVDS with this data mapping: LVDS_POWER (0x8726) = 0x3F LVDS_DIGITAL_CTRL (0x8728) = 0bUU00UU00, where U is user options.
On Chip Microcontroller: The FLI8532 on-chip micro-controller (OCM) serves as the system micro-controller. It programs the FLI8532 and manages other devices in the system such as the keypad and non-volatile RAM (NVRAM) using general-purpose input/output (GPIO) pins.
The two-wire protocol requires each slave device to be addressable by a 7-bit identification number. A two-wire data transfer consists of a stream of serially transmitted bytes formatted as shown in the figure below. A transfer is initiated (START) by a high-to-low transition on MSTR_SDA while MSTR_SCL is held high. A transfer is terminated by a STOP (a low-to-high transition on MSTR_SDA while MSTR_SCL is held high) or by a START (to begin another transfer).
Clock Generation The FLI8125 accepts the following input sources: 1.Crystal Input Clock (TCLK and XTAL). This is the input pair to an internal crystal oscillator and corresponding logic. Alternatively, a single ended TTL/CMOS clock input can be driven into the XTAL pin (leave TCLK as n/c in this case). 2.External Clocks on various GPIOs for test purposes 3.Host Interface Transfer Clock (SCL), I2C slave SCL for DDC2Bi and another SCL for Serial Inter-Processor Communication (SIPC) 4.Video Port VCLK 5.
Figure 8-8 FLI8125 Internally Synthesized Clocks Analog Front End The Analog Front End is responsible for selecting and capturing the desired analog input video stream. Overall application cost is reduced by providing analog switching capabilities for 16 separate analog signals. These signals are re-configurable as different combinations of composite, S-Video, YPrPb and RGB video streams depending upon the end application.
Figure 8-9 Analog Input Port The Analog Front End provides the capability to capture 16 analog video inputs which can be a combination of Composite (CVBS), S-Video (SY, SC), YPrPb (Y, Pr, Pb) or RGB (R, G, B). The Analog Source Selectors are responsible for switching the desired analog inputs to the ADCs for digitization. There are two types of switching required: Channel Selection, Fast Blank Switching.
Figure 8-10 Digital Datapath Digital Input Port The Digital Input Port is 24-bit input bus that can be connected to external DVI receivers, video decoders, etc. and is able to accept either 8-bit CCIR656 data, 16-bit 4:2:2 YUV data or 24-bit RGB data. For RGB input data, a selectable color space converter is used to transform RGB video input data from a DVI Rx to internal 16-bit 4:2:2 YUV.
Input Capture The Input Capture block is responsible for extracting valid data from the input data stream and creating the required synchronization signals required by the data pipeline. This block also provides stable timing when no stable input timing exists. The selected input data stream is cropped using a programmable input capture window. Only data within the programmable window is allowed through the data pipeline for subsequent processing. Data that lies outside of the window is ignored.
Image Processing The following figure shows the various image processing blocks that operate on the captured video data stream. Each block is individually selectable and can be removed from the processing chain via a selectable bypass path. When a processing block is bypassed, it automatically enters a low power mode to help reduce overall power consumption.
Display Output Interface The Display Output Port provides data and control signals that permit the connection to a variety of flat panel devices using a 24-bit TTL or LVDS interface. The output interface is configurable for single or dual wide LVDS in 18 or 24-bit RGB pixels format. All display data and timing signals are synchronous with the DCLK display clock.
Figure 8-13 Display Windows and Timing Data captured by the Input Capture Window and processed by the various image manipulation blocks is output in the Display Active Window. This window is always in the foreground and lies on top of all other output windows, except OSD overlay windows. Typically the Display Active Window is set to the same size as the output of the Scaling Engine. If the Display Active Window is set too small, then the bottom and right hand edges of the image data are cropped.
The benefit of dithering is that the eye tends to average neighboring pixels and a smooth image free of contours is perceived. Dithering works by spreading the quantization error over neighboring pixels both spatially and temporally. Two dithering algorithms are available: random or ordered dithering. Ordered dithering is recommended when driving a 6-bit panel.
Figure 8-14 FLI8125 OCM Programming The operation of HDMI Sil9011 The SiI 9011 provides one HDMI input port. The SiI 9011 video output goes to a video processor while the audio output goes to an audio DAC. CONFIDENTIAL – DO NOT COPY Page 8-17 File No.
Figure 8-15 HDMI 9011 Block Diagram TMDS Digital Core The core performs 10-to-8-bit TMDS decoding on the audio and video data received from the three TMDS differential data lines along with a TMDS differential clock. The TMDS core supports link clock rates to 165MHz, including CE modes to 720p/1080i/1080p and PC modes to XGA, SXGA and UXGA. Active Port Detection The PanelLink core detects an active TMDS clock and detects an actively toggling DE signal.
Data Input and Conversion Mode Control Logic The mode control logic determines if the decrypted data is video, audio or auxiliary information, and directs it to the appropriate logic block. Video Data Conversion and Video Output The SiI 9011 can output video in many different formats (see examples in Table 2). The receiver can also process the video data before it is output, as shown in Figure 5. Each of the processing blocks may be bypassed by setting the appropriate register bits.
Chapter 9 Waveforms 1. Ripple Voltage (1) PDP_+5Vsc (CN1.1) (2) PDP_+12V (CN1.7) CONFIDENTIAL – DO NOT COPY Page 9-1 File No.
(3) PDP_+5Vsb (CN3.4) (4) FLI8125 (U10) +3.3V_I/O_HUD CONFIDENTIAL – DO NOT COPY Page 9-2 File No.
+3.3V_ADC_HUD +1.8V_ADC_HUD CONFIDENTIAL – DO NOT COPY Page 9-3 File No.
(5) FLI8532 (U13) +3.3V_I/O +1.8V_ADC CONFIDENTIAL – DO NOT COPY Page 9-4 File No.
+2.5V_DDR +1.8V_CORE CONFIDENTIAL – DO NOT COPY Page 9-5 File No.
(6) NT5DS16M16CS-5T (U16, U17) (7) Am29LV320DT90-ED (XU1) CONFIDENTIAL – DO NOT COPY Page 9-6 File No.
(8) LM2660 (-5V_N of the U29) CONFIDENTIAL – DO NOT COPY Page 9-7 File No.
2. Clock Timing (1) NT5DS16M16CS-5T DDR clock (pin 45 of the U16 or U17) (2) FLI8125 Crystal clock (pin 15 of the U10) CONFIDENTIAL – DO NOT COPY Page 9-8 File No.
Hudson output clock (3) FLI8532 Crystal clock (pin B26 of the U13 or pin 1 of the C155) CONFIDENTIAL – DO NOT COPY Cortze output clock Page 9-9 File No.
(4) MSP4450G crystal clock (pin 55 of the U32) CONFIDENTIAL – DO NOT COPY Page 9-10 File No.
(5) SiI9011CLU crystal clock (pin 84 of the U35 and U42) (6) IC SM5964C40J crystal clock (pin 20 of the U38) CONFIDENTIAL – DO NOT COPY Page 9-11 File No.
3. Horizontal and Vertical sync. Timing (1) VGA input (1024x768x60Hz) H-sync CONFIDENTIAL – DO NOT COPY Page 9-12 File No.
V-sync CONFIDENTIAL – DO NOT COPY Page 9-13 File No.
(2) SiI9011CLU (U35 and U42) CLK BHS-sync CONFIDENTIAL – DO NOT COPY Page 9-14 File No.
BVS-sync CONFIDENTIAL – DO NOT COPY Page 9-15 File No.
CONFIDENTIAL – DO NOT COPY Page 9-16 File No.
Chapter 10 PDP Trouble Shooting A. SYSTEM OVERVIEW Power supply board Y driver board X driver board Main board Audio Voltage selectior Display board EMI filter Audio power IR board CONFIDENTIAL – DO NOT COPY Page 10-1 File No.
B.
DISPLAY BOARD IR BOARD CONFIDENTIAL – DO NOT COPY Page 10-3 File No.
PDP DISPLAY NOTHING 1.
PDP DISPLAY NOTHING(Analog HD1/AC on/off default) Start No Power LED is lighting? Check AC power cord Yes No Power LED is lighting? Yes Press Meun or Info. Is there any OSD’s logo Check input source No Check internal cable? 1.LVDS cable. No Check W1 pin 27 is high? (Display_ON) No No Remove R87. Check U13 pin AD14. Is AD14 high? U13 fail Yes No Power LED is lighting? No Check internal cable? 1.CN1’s cable 2.
PDP DISPLAY NOTHING(Analog HD1 without Pb signal) BLOCK 1 No No Check component 1 (Pb signal) ÎC259 Is there sync? Is picture on screen? Trace componect 1 from Input To U13 circuit Check R196,R198 Yes No Use GProbe connect from main to PC.
PDP DISPLAY NOTHING(Analog HD1 on PIP mode without Pb signal) BLOCK 1 No Is picture on screen? Check component 1 (Pb signal) ÎC255 Is there sync? No Trace componect 1 from Input To U10 circuit Check R200,R198 Yes No Use GProbe connect from main to PC.
PDP DISPLAY NOTHING(Analog HD2 without Pb signal) BLOCK 1 No Is no blue color on screen? Check component 2 (Pb signal) ÎC260,R197 Is there sync? No Yes Check U23 outnputÎpin 28 InputÎ pin 15 Input clamp voltageÎpin 5(+5V) Output clamp voltageÎpin 29(+5V) VCC3Îpin 22,23(+5V) Input_switch_selectÎhigh(+5V) Yes No Use GProbe connect from main to PC. Does scaler detect the signal? U13 fail No U23 fail Check before U23’s circuit 1.C268,C269(AC coupled) 2.R211 3.
PDP DISPLAY NOTHING(Analog HD2 on PIP mode without Pb signal) BLOCK 1 No Is no blue color on screen? Check U24 outnputÎpin 28 InputÎ pin 15 Input clamp voltageÎpin 5(+5V) Output clamp voltageÎpin 29(+5V) VCC3Îpin 22,23(+5V) Input_switch_selectÎhigh(+5V) No Check component 2 (Pb signal) ÎC288,R213 Is there sync? Yes Yes No Use GProbe connect from main to PC. Does scaler detect the signal? No U24 fail Check before U24’s circuit 1.C289,C290(AC coupled) 2.R211 3.
PDP DISPLAY NOTHING(RGB on PIP mode without screen) BLOCK 1 No Is picture on screen? Check U45 H sync output Î U45 pin4,R181 V sync output Î U45 pin8,R184 Is there signal? No Check U45 H sync input Î U45 pin1,R185 V sync input Î U45 pin5,R187 Yes Check U45 pin 14Î +3.3V Yes U45 fail No Check input source Yes Check U22’s signal output R signal ÎC233,R180,R169,U22.34 G signal ÎC232,R177,R171,U22.31 B signal ÎC231,R174,R176,U22.
PDP DISPLAY NOTHING(Composite 1 without screen) BLOCK 1 No Is picture on screen? No Check C310,R275,R274 Is there signal? Check Q28’s emitter. Is there signal? No Check Q28’s Base. Is there signal? Check collector voltage(+5V). No Q28 fail Yes No Use GProbe connect from main to PC. Does scaler detect the signal? Q13 fail Yes Check: 1.C309 (signal AC coupled) 2.R276 3.
PDP DISPLAY NOTHING(Composite 2 without screen) BLOCK 1 No Is picture on screen? No Check C316,R286,R285 Is there signal? Check Q29’s emitter. Is there signal? No Check Q29’s Base. Is there signal? Check collector voltage(+5V). No Q29 fail Yes No Use GProbe connect from main to PC. Does scaler detect the signal? Q13 fail Yes Check: 1.C315 (signal AC coupled) 2.R282 3.
PDP DISPLAY NOTHING(S-VIDEO 1 without screen) BLOCK 1 No Is picture on screen? No Check C320,R293,R292 Is there signal? Check Q30’s emitter. Is there signal? No Check Q30’s Base. Is there signal? Check collector voltage(+5V). No Check Q31’s Base. Is there signal? Check collector voltage(+5V). No Q30 fail Yes No Use GProbe connect from main to PC. Does scaler detect the signal? Q13 fail Yes Check: 1.C319 (signal AC coupled) 2.R297 3.
PDP DISPLAY NOTHING(S-VIDEO 1 on PIP mode without screen) BLOCK 1 No Is picture on screen? No Check C318,R291,R292 Is there signal? Check Q30’s emitter. Is there signal? No Check Q30’s Base. Is there signal? Check collector voltage(+5V). No Check Q31’s Base. Is there signal? Check collector voltage(+5V). No Q30 fail Yes No Use GProbe connect from main to PC. Does scaler detect the signal? Q10 fail Yes Check: 1.C319 (signal AC coupled) 2.R297 3.
PDP DISPLAY NOTHING(S-VIDEO 2 without screen) BLOCK 1 No Is picture on screen? No Check C332,R316,R320 Is there signal? Check Q33’s emitter. Is there signal? No Check Q33’s Base. Is there signal? Check collector voltage(+5V). No Check Q32’s Base. Is there signal? Check collector voltage(+5V). No Q33 fail Yes No Use GProbe connect from main to PC. Does scaler detect the signal? U13 fail Yes Check: 1.C335 (signal AC coupled) 2.R300 3.
PDP DISPLAY NOTHING(S-VIDEO 2 on PIP mode without screen) BLOCK 1 No Is picture on screen? No Check C331,R313,R320 Is there signal? Check Q33’s emitter. Is there signal? No Check Q33’s Base. Is there signal? Check collector voltage(+5V). No Check Q32’s Base. Is there signal? Check collector voltage(+5V). No Q33 fail Yes No Use GProbe connect from main to PC. Does scaler detect the signal? U10 fail Yes Check: 1.C335 (signal AC coupled) 2.R300 3.
PDP DISPLAY NOTHING(Digital 2 U35 with PORT B without screen) BLOCK 1 No Check input source? Is picture on screen? Yes Check U37 I2C bus SCLÎPin 6 SDAÎpin 5 No Is picture on screen? Check U35 pin 90 Î high V syncÎR419 H syncÎR420 clockÎR421 No No No Check U37 power 5VÎPin 8 Check +3.3V_SWÎ FB19,FB20,FB21,FB22 U41Î+1.8V_HDMI1 Check D66 and D65 Are there 5V output? Yes No D66 fail or D65 fail Check crystalÎ Y2=28.322MHz Yes Check Q44 sourceÎhigh(3.
Block 2 start HDMI’s chip communicate with SM5964,is ok? No Check U38’s powerÎ Pin 44,35 No Check U2’s +5V_SW Îpin 7,8 Yes Check Y3Î 11.0592MHz Yes Check U38’s UART TxDÎpin 13 RxDÎpin 11 No Check U20Î pin 16Î+5V Pin 10Îoutput select=high No U20 fail Yes No Check R143,R144 U13 fail 15 CONFIDENTIAL – DO NOT COPY Page10-18 File No.
TROUBLE OF DDC READING Start No Support DDC2B 1.Analog cable ok? 2.Voltage of +5V_BUF ok? 3.Check U21 4.Is compliant protocol? No Support DDC2B 1.HDMI cable ok? 2.Voltage of VCC5_E2P_2ok? 3.Check U44 4.Is compliant protocol? No Support DDC2B 1.HDMI cable ok? 2.Voltage of VCC5_E2P_1 ok? 3.Check U37 4.Is compliant protocol? Analog DDC OK? Yes Digital HDMI1 DDC OK? Yes Digital HDMI2 DDC OK? End CONFIDENTIAL – DO NOT COPY Page10-19 File No.
