Specifications

DP83848C , DP83848I
DP83848VYB, DP83848YB
www.ti.com SNLS266E –MAY 2007–REVISED MARCH 2015
SIGNAL NAME TYPE PIN # DESCRIPTION
PHYAD0 (COL) S, O, PU 42 PHY ADDRESS [4:0]: The DP83848VYB provides five PHY address pins, the state of
PHYAD1 (RXD1_0) S, O, PD 43 which are latched into the PHYCTRL register at system Hardware-Reset.
PHYAD2 (RXD0_1) 44 The DP83848VYB supports PHY Address strapping values 0 (<00000>) through 31
PHYAD3 (RXD1_2) 45 (<11111>).A PHY Adress of 0 puts the part into the Mll isolate Mode. The Mll isolate
PHYAD4 (RXD1_3) 46 mode must be selected by strapping Phy Address 0; changing to Address 0 by register
write will not put the Phy in the Mll isolate mode. Please refer to Section 6.4.5 for
additional information.
PHYAD0 pin has weak internal pullup resistor.
PHYAD[4:1] pins have weak internal pulldown resistors.
AN_EN(LED_ACT/COL) S, O, PU 26 Auto-Negotiation Enable: When high, this enables Auto-Negotiation with the capability
AN_1 (LED_SPEED) 27 set by AN0 and AN1 pins. When low, this puts the part into Forced Mode with the
AN_0 (LED_LINK) 28 capability set by AN0 and AN1 pins.
AN0 / AN1: These input pins control the forced or advertised operating mode of the
DP83848VYB according to the following table. The value on these pins is set by
connecting the input pins to GND (0) or V
CC
(1) through 2.2 kΩ resistors. These pins
should NEVER be connected directly to GND or V
CC
.
The value set at this input is latched into the DP83848VYB at Hardware-Reset.
The float/pulldown status of these pins are latched into the Basic Mode Control Register
and the Auto_Negotiation Advertisement Register during Hardware-Reset.
The default is 111 since the these pin have internal pullups.
AN_EN AN1 AN0 Forced Mode
0 0 0 10BASE-T, Half-Duplex
0 0 1 10BASE-T, Full-Duplex
0 1 0 100BASE-TX, Half-Duplex
0 1 1 100BASE-TX, Full-Duplex
AN_EN AN1 AN0 Advertised Mode
1 0 0 10BASE-T, Half/Full-Duplex
1 0 1 100BASE-TX, Half/Full-Duplex
1 1 0 10BASE-T, Half-Duplex,
100BASE-TX, Half-Duplex
1 1 1 10BASE-T, Half/Full-Duplex,
100BASE-TX, Half/Full-Duplex
MII_MODE (RX_DV) S, O, PD 39 MII MODE SELECT: This strapping option pair determines the operating mode of the
SNI_MODE (TXD_3) 6 MAC Data Interface. Default operation (No pullups) will enable normal MII Mode of
operation. Strapping MII_MODE high will cause the device to be in RMII or SNI modes of
operation, determined by the status of the SNI_MODE strap. Since the pins include
internal pulldowns, the default values are 0.
The following table details the configurations:
MII_MODE SNI_MODE MAC Interface Mode
0 X MII Mode
1 0 RMII Mode
1 1 10 Mb SNI Mode
LED_CFG (CRS) S, O, PU 40 LED CONFIGURATION: This strapping option determines the mode of operation of the
LED pins. Default is Mode 1. Mode 1 and Mode 2 can be controlled through the strap
option. All modes are configurable through register access.
See Table 6-2 for LED Mode Selection.
MDIX_EN (RX_ER) S, O, PU 41 MDIX ENABLE: Default is to enable MDIX. This strapping option disables Auto-MDIX. An
external pulldown will disable Auto-MDIX mode.
4.10 10 Mb/s and 100 Mb/s PMD Interface
SIGNAL NAME TYPE PIN # DESCRIPTION
TD-, TD+ I/O 16 Differential common driver transmit output (PMD Output Pair). These differential outputs
17 are automatically configured to either 10BASE-T or 100BASE-TX signaling.
IIn Auto-MDIX mode of operation, this pair can be used as the Receive Input pair.
These pins require 3.3-V bias for operation.
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