Specifications
DP83848C
,
DP83848I
DP83848VYB, DP83848YB
SNLS266E –MAY 2007–REVISED MARCH 2015
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4.6 LED Interface
See Table 6-2 for LED Mode Selection.
SIGNAL NAME TYPE PIN # DESCRIPTION
LED_LINK S, O, PU 28 LINK LED: In Mode 1, this pin indicates the status of the LINK. The LED will be
ON when Link is good.
LINK/ACT LED: In Mode 2 and Mode 3, this pin indicates transmit and receive
activity in addition to the status of the Link. The LED will be ON when Link is
good. It will blink when the transmitter or receiver is active.
LED_SPEED S, O, PU 27 SPEED LED: The LED is ON when device is in 100 Mb/s and OFF when in 10
Mb/s. Functionality of this LED is independent of mode selected.
LED_ACT/COL S, O, PU 26 ACTIVITY LED: In Mode 1, this pin is the Activity LED which is ON when activity
is present on either Transmit or Receive.
COLLISION/DUPLEX LED: In Mode 2, this pin by default indicates Collision
detection. For Mode 3, this LED output may be programmed to indicate Full-
duplex status instead of Collision.
4.7 JTAG Interface for DP83848I/VYB/YB
SIGNAL NAME TYPE PIN #
(1)
DESCRIPTION
TCK I, PU 8 TEST CLOCK
This pin has a weak internal pullup.
TDI I, PU 12 TEST DATA INPUT
This pin has a weak internal pullup.
TDO O 9 TEST OUTPUT
TMS I, PU 10 TEST MODE SELECT
This pin has a weak internal pullup.
TRST# I, PU 11 TEST RESET: Active low asynchronous test reset.
This pin has a weak internal pullup.
(1) DP83848C does not support JTAG. Pins 8-12 should be left unconnected.
4.8 Reset and Power Down
SIGNAL NAME TYPE PIN # DESCRIPTION
RESET_N I, PU 29 RESET: Active Low input that initializes or re-initializes the DP83848VYB. Asserting
this pin low for at least 1 µs will force a reset process to occur. All internal registers
will re-initialize to their default states as specified for each bit in the Section 6.6
section. All strap options are re-initialized as well.
PWR_DOWN/INT I, PU 7 See Section 7.2.1.3.1 for detailed description.
The default function of this pin is POWER DOWN.
POWER DOWN: The pin is an active low input in this mode and should be
asserted low to put the device in a Power Down mode.
INTERRUPT: The pin is an open drain output in this mode and will be asserted low
when an interrupt condition occurs. Although the pin has a weak internal pullup,
some applications may require an external pullup resister. Register access is
required for the pin to be used as an interrupt mechanism. See Section 7.2.1.3.1.2
for more details on the interrupt mechanisms.
4.9 Strap Options
The DP83848VYB uses many of the functional pins as strap options. The values of these pins are
sampled during reset and used to strap the device into specific modes of operation. The strap option pin
assignments are defined below. The functional pin name is indicated in parentheses.
A 2.2 kΩ resistor should be used for pulldown or pullup to change the default strap option. If the default
option is required, then there is no need for external pullup or pulldown resistors. Since these pins may
have alternate functions after reset is deasserted, they should not be connected directly to V
CC
or GND.
8 Pin Configuration and Functions Copyright © 2007–2015, Texas Instruments Incorporated
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