Specifications

PHY
Component
Optional 0 :
or Bead
Ground Pin
Vdd
Pin
PCB Via
Vdd
PCB
Via
0.1 PF
Plane Coupling
Component
PHY
Component
Note:Power/
Ground Planes
Voided under
Transformer
RJ45
Connector
Transformer
(if not
Integrated in
RJ45)
System Power/Ground
Planes
Chassis Ground
Plane
Termination
Components
Plane Coupling
Component
DP83848C , DP83848I
DP83848VYB, DP83848YB
SNLS266E –MAY 2007–REVISED MARCH 2015 www.ti.com
7.3.2 Layout Example
Figure 7-15. Layout Example
7.4 Power Supply Recommendations
The device Vdd supply pins should be bypassed with low impedance 0.1-μF surface mount capacitors. To
reduce EMI, the capacitors should be places as close as possible to the component Vdd supply pins,
preferably between the supply pins and the vias connecting to the power plane. In some systems it may
be desirable to add 0-Ω resistors in series with supply pins, as the resistor pads provide flexibility if adding
EMI beads becomes necessary to meet system level certification testing requirements. (See Figure 6.8) It
is recommended the PCB have at least one solid ground plane and one solid Vdd plane to provide a low
impedance power source to the component. This also provides a low impedance return path for non-
differential digital MII and clock signals. A 10.0-μF capacitor should also be placed near the PHY
component for local bulk bypassing between the Vdd and ground planes.
Figure 7-16. Vdd Bypass Layout
78 Application, Implementation, and Layout Copyright © 2007–2015, Texas Instruments Incorporated
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