Specifications

DP83848C , DP83848I
DP83848VYB, DP83848YB
SNLS266E –MAY 2007–REVISED MARCH 2015 www.ti.com
7.3 Layout
7.3.1 Layout Guidelines
7.3.1.1 PCB Layout Considerations
Place the 49.9-Ω,1% resistors and 0.1-μF decoupling capacitor near the PHYTER TD± and RD± pins and
via directly to the Vdd plane.
Stubs should be avoided on all signal traces, especially the differential signal pairs. See Figure 7-11.
Within the pairs (for example, TD+ and TD-) the trace lengths should be run parallel to each other and
matched in length. Matched lengths minimize delay differences, avoiding an increase in common mode
noise and increased EMI. See Figure 7-11.
Figure 7-11. Differential Signal Pair – Stubs
Ideally, there should be no crossover or via on the signal paths. Vias present impedance discontinuities
and should be minimized. Route an entire trace pair on a single layer if possible.
PCB trace lengths should be kept as short as possible.
Signal traces should not be run such that they cross a plane split. See Figure 7-12. A signal crossing a
plane split may cause unpredictable return path currents and would likely impact signal quality as well,
potentially creating EMI problems.
Figure 7-12. Differential Signal Pair-Plane Crossing
MDI signal traces should have 50 Ω to ground or 100 Ω differential controlled impedance. Many tools are
available online to calculate this.
76 Application, Implementation, and Layout Copyright © 2007–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DP83848C DP83848I DP83848VYB DP83848YB