Specifications

DP83848C , DP83848I
DP83848VYB, DP83848YB
SNLS266E –MAY 2007–REVISED MARCH 2015 www.ti.com
Figure 7-3. Crystal Oscillator Circuit
Table 7-1. 25-MHz Oscillator Specification
PARAMETER CONDITION MIN TYP MAX UNIT
Frequency 25 MHz
Frequency Tolerance Operational Temperature ±50 ppm
Frequency Stability 1 year aging ±50 ppm
Rise / Fall Time 20% - 80% 6 nsec
Jitter Short term 800
(1)
psec
Jitter Long term 800
(1)
psec
Symmetry Duty Cycle 40% 60%
(1) This limit is provided as a guideline for component selection and not specified by production testing. Refer to AN-1548 (SNLA091),
PHYTER 100 Base-TX Reference Clock Jitter Tolerance, for details on jitter performance.
Table 7-2. 50-MHz Oscillator Specification
PARAMETER CONDITION MIN TYP MAX UNIT
Frequency 50 MHz
Frequency Tolerance Operational Temperature ±50 ppm
Frequency Stability Operational Temperature ±50 ppm
Rise / Fall Time 20% - 80% 6 nsec
Jitter Short term 800
(1)
psec
Jitter Long term 800
(1)
psec
Symmetry Duty Cycle 40% 60%
(1) This limit is provided as a guideline for component selection and not specified by production testing. Refer to AN-1548 (SNLA091),
PHYTER 100 Base-TX Reference Clock Jitter Tolerance for details on jitter performance.
Table 7-3. 25-MHz Crystal Specification
PARAMETER CONDITION MIN TYP MAX UNIT
Frequency 25 MHz
Frequency Tolerance Operational Temperature ±50 ppm
Frequency Stability 1 year aging ±50 ppm
Load Capacitance 25 40 pF
7.2.1.3 Power Feedback Circuit
To ensure correct operation for the DP83848VYB, parallel caps with values of 10 µF and 0.1 µF should be
placed close to pin 23 (PFBOUT) of the device.
Pin 18 (PFBIN1), pin 37 (PFBIN2), pin 23 (PFBIN3) and pin 54 (PFBIN4) must be connected to pin 31
(PFBOUT), each pin requires a small capacitor (.1 µF). See Figure 7-4 below for proper connections.
70 Application, Implementation, and Layout Copyright © 2007–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DP83848C DP83848I DP83848VYB DP83848YB