Specifications
1:1
1:1
RJ45
NOTE: CENTER TAP IS PULLED TO VDD
*PLACE CAPACITORS CLOSE TO THE
TRANSFORMER CENTER TAPS
RD-
RD+
TD-
TD+
0.1 PF*
0.1 PF*
COMMON MODE CHOKES
MAY BE REQUIRED
0.1 PF
0.1 PF
Vdd
Vdd
Vdd
All values are typical and are +/- 1%
49.9 :
49.9 :
49.9 :
49.9 :
PLACE RESISTORS AND
CAPACITORS CLOSE TO
THE DEVICE
TPRDM
TDRDP
TPTDM
TPTDP
T1
DP83848C
,
DP83848I
DP83848VYB, DP83848YB
www.ti.com
SNLS266E –MAY 2007–REVISED MARCH 2015
Figure 7-2. 10/100 Mb/s Twisted Pair Interface
7.2.1.2 Clock IN (X1) Requirements
The DP83848VYB supports an external CMOS level oscillator source or a crystal resonator device.
7.2.1.2.1 Oscillator
If an external clock source is used, X1 should be tied to the clock source and X2 should be left floating.
Specifications for CMOS oscillators: 25 MHz in MII Mode and 50 MHz in RMII Mode are listed in Table 7-1
and Table 7-2.
7.2.1.2.2 Crystal
A 25-MHz, parallel, 20-pF load crystal resonator should be used if a crystal source is desired. Figure 7-4
shows a typical connection for a crystal resonator circuit. The load capacitor values will vary with the
crystal vendors; check with the vendor for the recommended loads.
The oscillator circuit is designed to drive a parallel resonance AT cut crystal with a minimum drive level of
100 mW and a maximum of 500 µW. If a crystal is specified for a lower drive level, a current limiting
resistor should be placed in series between X2 and the crystal.
As a starting point for evaluating an oscillator circuit, if the requirements for the crystal are not known, C
L1
and C
L2
should be set at 33 pF, and R
1
should be set at 0 Ω.
Specification for 25-MHz crystal are listed in Table 7-3.
Copyright © 2007–2015, Texas Instruments Incorporated Application, Implementation, and Layout 69
Submit Documentation Feedback
Product Folder Links: DP83848C DP83848I DP83848VYB DP83848YB