Specifications

DP83848C , DP83848I
DP83848VYB, DP83848YB
www.ti.com SNLS266E –MAY 2007–REVISED MARCH 2015
Table 6-26. PHY Control Register (PHYCR), address 0x19h (continued)
Bit Bit Name Default Description
6 LED_CNFG[1] 0, RW LED Configuration
5 LED_CNFG[0] Strap, RW
LED_CNFG[1] LED_CNFG[0] Mode Description
Don't care 1 Mode 1
0 0 Mode 2
1 0 Mode 3
In Mode 1, LEDs are configured as follows:
LED_LINK = ON for Good Link, OFF for No Link
LED_SPEED = ON in 100 Mb/s, OFF in 10 Mb/s
LED_ACT/LED_COL = ON for Activity, OFF for No Activity
In Mode 2, LEDs are configured as follows:
LED_LINK = ON for good Link, BLINK for Activity
LED_SPEED = ON in 100 Mb/s, OFF in 10 Mb/s
LED_ACT/LED_COL = ON for Collision, OFF for No Collision
Full Duplex, OFF for Half Duplex
In Mode 3, LEDs are configured as follows:
LED_LINK = ON for Good Link, BLINK for Activity
LED_SPEED = ON in 100 Mb/s, OFF in 10 Mb/s
LED_ACT/LED_COL = ON for Full Duplex, OFF for Half Duplex
4:0 PHYADDR[4:0] Strap, RW PHY Address: PHY address for port.
6.6.1.2.10 10 Base-T Status/Control Register (10BTSCR)
This register is used for control and status for 10BASE-T device operation.
Table 6-27. 10Base-T Status/Control Register (10BTSCR), address 1Ah
Bit Bit Name Default Description
15 10BT_SERIAL Strap, RW 10Base-T Serial Mode (SNI)
1 = Enables 10Base-T Serial Mode.
0 = Normal Operation.
Places 10 Mb/s transmit and receive functions in Serial Network Interface (SNI)
Mode of operation. Has no effect on 100 Mb/s operation.
14:1 RESERVED 0, RW RESERVED: Must be zero.
2
11:9 SQUELCH 100, RW Squelch Configuration:
Used to set the Squelch ON threshold for the receiver.
Default Squelch ON is 330mV peak.
8 LOOPBACK_10_DIS 0, RW 10Base-T Loopback Disable:
In half-duplex mode, default 10BASE-T operation loops Transmit data to the
Receive data in addition to transmitting the data on the physical medium. This is
for consistency with earlier 10BASE2 and 10BASE5 implementations which used
a shared medium. Setting this bit disables the loopback function.
This bit does not affect loopback due to setting BMCR[14].
7 LP_DIS 0, RW Normal Link Pulse Disable:
1 = Transmission of NLPs is disabled.
0 = Transmission of NLPs is enabled.
6 FORCE_LINK_10 0, RW Force 10Mb Good Link:
1 = Forced Good 10Mb Link.
0 = Normal Link Status.
5 RESERVED 0, RW RESERVED: Must be zero.
4 POLARITY RO/LH 10Mb Polarity Status:
This bit is a duplication of bit 12 in the PHYSTS register. Both bits will be cleared
upon a read of 10BTSCR register, but not upon a read of the PHYSTS register.
1 = Inverted Polarity detected.
0 = Correct Polarity detected.
Copyright © 2007–2015, Texas Instruments Incorporated Detailed Description 65
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