Specifications

DP83848C , DP83848I
DP83848VYB, DP83848YB
www.ti.com SNLS266E –MAY 2007–REVISED MARCH 2015
6.6.1.2.7 RMII and Bypass Register (RBR)
This register configures the RMII Mode of operation. When RMII mode is disabled, the RMII functionality is
bypassed.
Table 6-24. RMII and Bypass Register (RBR), addresses 0x17h
Bit Bit Name Default Description
15:6 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
5 RMII_MODE Strap, RW Reduced MII Mode:
0 = Standard MII Mode.
1 = Reduced MII Mode.
4 RMII_REV1_0 0, RW Reduced MII Revision 1.0:
0 = (RMII revision 1.2) CRS_DV will toggle at the end of a packet to indicate
deassertion of CRS.
1 = (RMII revision 1.0) CRS_DV will remain asserted until final data is transferred.
CRS_DV will not toggle at the end of a packet.
3 RX_OVF_STS 0, RO RX FIFO Over Flow Status:
0 = Normal.
1 = Overflow detected.
2 RX_UNF_STS 0, RO RX FIFO Under Flow Status:
0 = Normal.
1 = Underflow detected.
1:0 ELAST_BUF[1:0] 01, RW Receive Elasticity Buffer:
This field controls the Receive Elasticity Buffer which allows for frequency variation
tolerance between the 50 MHz RMII clock and the recovered data. The following
values indicate the tolerance in bits for a single packet. The minimum setting
allows for standard Ethernet frame sizes at ±50ppm accuracy for both RMII and
Receive clocks. For greater frequency tolerance the packet lengths may be scaled
(for example, for ±100ppm, the packet lenths need to be divided by 2).
00 = 14 bit tolerance (up to 16800 byte packets)
01 = 2bit tolerance (up to 2400 byte packets)
10 = 6bit tolerance (up to 7200 byte packets)
11 = 10 bit tolerance (up to 12000 byte packets)
6.6.1.2.8 LED Direct Control Register (LEDCR)
This register provides the ability to directly control any or all LED outputs. It does not provide read access
to LEDs.
Table 6-25. LED Direct Control Register (LEDCR), address 0x18h
Bit Bit Name Default Description
15:6 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
5 DRV_SPDLED 0, RW 1 = Drive value of SPDLED bit onto LED_SPEED output.
0 = Normal operation.
4 DRV_LNKLED 0, RW 1 = Drive value of LNKLED bit onto LED_LINK output.
0 = Normal operation.
3 DRV_ACTLED 0, RW 1 = Drive value of ACTLED bit onto LED_ACT/LED_COL output.
0 = Normal operation.
2 SPDLED 0, RW Value to force on LED_SPEED output.
1 LNKLED 0, RW Value to force on LED_LINK output.
0 ACTLED 0, RW Value to force on LED_ACT/LED_COL output.
Copyright © 2007–2015, Texas Instruments Incorporated Detailed Description 63
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