Specifications

DP83848C , DP83848I
DP83848VYB, DP83848YB
SNLS266E –MAY 2007–REVISED MARCH 2015 www.ti.com
6.6.1.2.6 100 Mb/s PCS Configuration and Status Register (PCSR)
This register contains control and status information for the 100BASE Physical Coding Sublayer.
Table 6-23. 100 Mb/s PCS Configuration and Status Register (PCSR), address 0x16h
Bit Bit Name Default Description
15:13 RESERVED <00>, RO RESERVED: Writes ignored, read as 0.
12 RESERVED 0 RESERVED:Must be zero.
11 FREE_CLK 0, RW Receive Clock:
10 TQ_EN 0, RW 100Mbs True Quiet Mode Enable:
1 = Transmit True Quiet Mode.
0 = Normal Transmit Mode.
9 SD FORCE PMA 0, RW Signal Detect Force PMA:
1 = Forces Signal Detection in PMA.
0 = Normal SD operation.
8 SD_OPTION 1, RW Signal Detect Option:
1 = Default operation. Link will be asserted following detection of valid signal level
and Descrambler Lock. Link will be maintained as long as signal level is valid. A loss
of Descrambler Lock will not cause Link Status to drop.
0 = Modified signal detect algorithm. Link will be asserted following detection of valid
signal level and Descrambler Lock. Link will be maintained as long as signal level is
valid and Descrambler remains locked.
7 DESC_TIME 0, RW Descrambler Timeout:
Increase the descrambler timeout. When set this should allow the device to receive
larger packets (>9k bytes) without loss of synchronization.
1 = 2ms.
0 = 722us (per ANSI X3.263: 1995 (TP-PMD) 7.2.3.3e).
6 RESERVED 0 RESERVED: Must be zero.
5 FORCE_100_OK 0, RW Force 100 Mb/s Good Link:
1 = Forces 100 Mb/s Good Link.
0 = Normal 100 Mb/s operation.
4 RESERVED 0 RESERVED:Must be zero.
3 RESERVED 0 RESERVED:Must be zero.
2 NRZI_BYPASS 0, RW NRZI Bypass Enable:
1 = NRZI Bypass Enabled.
0 = NRZI Bypass Disabled.
1 RESERVED 0 RESERVED:Must be zero.
0 RESERVED 0 RESERVED:Must be zero.
62 Detailed Description Copyright © 2007–2015, Texas Instruments Incorporated
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