Specifications

DP83848C , DP83848I
DP83848VYB, DP83848YB
www.ti.com SNLS266E –MAY 2007–REVISED MARCH 2015
Table 6-20. MII Interrupt Status and Misc. Control Register (MISR), address 0x12h (continued)
Bit Bit Name Default Description
10 ANC_INT 0, RO/COR Auto-Negotiation Complete interrupt:
1 = Auto-negotiation complete interrupt is pending and is cleared by the current
read.
0 = No Auto-negotiation complete interrupt pending.
9 FHF_INT 0, RO/COR False Carrier Counter half-full interrupt:
1 = False carrier counter half-full interrupt is pending and is cleared by the current
read.
0 = No false carrier counter half-full interrupt pending.
8 RHF_INT 0, RO/COR Receive Error Counter half-full interrupt:
1 = Receive error counter half-full interrupt is pending and is cleared by the current
read.
0 = No receive error carrier counter half-full interrupt pending.
7 Reserved 0, RW Enable Interrupt on Link Quality Monitor event.
6 ED_INT_EN 0, RW Enable Interrupt on energy detect event.
5 LINK_INT_EN 0, RW Enable Interrupt on change of link status.
4 SPD_INT_EN 0, RW Enable Interrupt on change of speed status.
3 DUP_INT_EN 0, RW Enable Interrupt on change of duplex status.
2 ANC_INT_EN 0, RW Enable Interrupt on Auto-negotiation complete event.
1 FHF_INT_EN 0, RW Enable Interrupt on False Carrier Counter Register half-full event.
0 RHF_INT_EN 0, RW Enable Interrupt on Receive Error Counter Register half-full event.
6.6.1.2.4 False Carrier Sense Counter Register (FCSCR)
This counter provides information required to implement the “False Carriers” attribute within the MAU
managed object class of Clause 30 of the IEEE 802.3 specification.
Table 6-21. False Carrier Sense Counter Register (FCSCR), address 0x14h
Bit Bit Name Default Description
15:8 RESERVED 0, RO RESERVED: Writes ignored, read as 0
7:0 FCSCNT[7:0] 0, RO/COR False Carrier Event Counter:
This 8-bit counter increments on every false carrier event. This counter sticks when
it reaches its max count (FFh).
6.6.1.2.5 Receiver Error Counter Register (RECR)
This counter provides information required to implement the “Symbol Error During Carrier” attribute within
the PHY managed object class of Clause 30 of the IEEE 802.3 specification.
Table 6-22. Receiver Error Counter Register (RECR), address 0x15h
Bit Bit Name Default Description
15:8 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
7:0 RXERCNT[7:0] 0, RO/COR RX_ER Counter:
When a valid carrier is present and there is at least one occurrence of an invalid
data symbol, this 8-bit counter increments for each receive error detected. This
event can increment only once per valid carrier event. If a collision is present, the
attribute will not increment. The counter sticks when it reaches its max count.
Copyright © 2007–2015, Texas Instruments Incorporated Detailed Description 61
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