Specifications

DP83848C , DP83848I
DP83848VYB, DP83848YB
SNLS266E –MAY 2007–REVISED MARCH 2015 www.ti.com
6.6.1.2.2 MII Interrupt Control Register (MICR)
This register implements the MII Interrupt PHY Specific Control register. Sources for interrupt generation
include: Energy Detect State Change, Link State Change, Speed Status Change, Duplex Status Change,
Auto-Negotiation Complete or any of the counters becoming half-full. The individual interrupt events must
be enabled by setting bits in the MII Interrupt Status and Event Control Register (MISR).
Table 6-19. MII Interrupt Control Register (MICR), address 0x11h
Bit Bit Name Default Description
15:3 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
2 TINT 0, RW Test Interrupt:
Forces the PHY to generate an interrupt to facilitate interrupt testing. Interrupts will
continue to be generated as long as this bit remains set.
1 = Generate an interrupt.
0 = Do not generate interrupt.
1 INTEN 0, RW Interrupt Enable:
Enable interrupt dependent on the event enables in the MISR register.
1 = Enable event based interrupts.
0 = Disable event based interrupts.
0 INT_OE 0, RW Interrupt Output Enable:
Enable interrupt events to signal through the PWRDOWN_INT pin by configuring
the PWRDOWN_INT pin as an output.
1 = PWRDOWN_INT is an Interrupt Output.
0 = PWRDOWN_INT is a Power Down Input.
6.6.1.2.3 MII Interrupt Status and Misc. Control Register (MISR)
This register contains event status and enables for the interrupt function. If an event has occurred since
the last read of this register, the corresponding status bit will be set. If the corresponding enable bit in the
register is set, an interrupt will be generated if the event occurs. The MICR register controls must also be
set to allow interrupts. The status indications in this register will be set even if the interrupt is not enabled.
Table 6-20. MII Interrupt Status and Misc. Control Register (MISR), address 0x12h
Bit Bit Name Default Description
15 Reserved 0, RO/COR Link Quality interrupt:
1 = Link Quality interrupt is pending and is cleared by the current read.
0 = No Link Quality interrupt pending.
14 ED_INT 0, RO/COR Energy Detect interrupt:
1 = Energy detect interrupt is pending and is cleared by the current read.
0 = No energy detect interrupt pending.
13 LINK_INT 0, RO/COR Change of Link Status interrupt:
1 = Change of link status interrupt is pending and is cleared by the current read.
0 = No change of link status interrupt pending.
12 SPD_INT 0, RO/COR Change of speed status interrupt:
1 = Speed status change interrupt is pending and is cleared by the current read.
0 = No speed status change interrupt pending.
11 DUP_INT 0, RO/COR Change of duplex status interrupt:
1 = Duplex status change interrupt is pending and is cleared by the current read.
0 = No duplex status change interrupt pending.
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