Specifications
DP83848C
,
DP83848I
DP83848VYB, DP83848YB
SNLS266E –MAY 2007–REVISED MARCH 2015
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4.2 Package Pin Assignments
VBH48A PIN # PIN NAME VBH48A PIN # PIN NAME
1 TX_CLK 26 LED_ACT/COL/AN_EN
2 TX_EN 27 LED_SPEED/AN1
3 TXD_0 28 LED_LINK/AN0
4 TXD_1 29 RESET_N
5 TXD_2 30 MDIO
6 TXD_3/SNI_MODE 31 MDC
7 PWR_DOWN/INT 32 IOVDD33
8 TCK 33 X2
9 TDO 34 X1
10 TMS 35 IOGND
11 TRST# 36 DGND
12 TDI 37 PFBIN2
13 RD - 38 RX_CLK
14 RD + 39 RX_DV/MII_MODE
15 AGND 40 CRS/CRS_DV/LED_CFG
16 TD - 41 RX_ER/MDIX_EN
17 TD + 42 COL/PHYAD0
18 PFBIN1 43 RXD_0/PHYAD1
19 AGND 44 RXD_1/PHYAD2
20 RESERVED 45 RXD_2/PHYAD3
21 RESERVED 46 RXD_3/PHYAD4
22 AVDD33 47 IOGND
23 PFBOUT 48 IOVDD33
24 RBIAS 49 GNDPAD
25 CLK_OUT
4.3 Serial Management Interface
SIGNAL TYPE PIN # DESCRIPTION
NAME
MDC I 31 MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO management data input/output
serial interface which may be asynchronous to transmit and receive clocks. The maximum clock
rate is 25 MHz with no minimum clock rate.
MDIO I/O 30 MANAGEMENT DATA I/O: Bi-directional management instruction/data signal that may be
sourced by the station management entity or the PHY. This pin requires a 1.5 kΩ pullup resistor.
4.4 Mac Data Interface
SIGNAL TYPE PIN # DESCRIPTION
NAME
TX_CLK O 1 MII TRANSMIT CLOCK: 25 MHz Transmit clock output in 100 Mb/s mode or 2.5 MHz in 10 Mb/s
mode derived from the 25 MHz reference clock.
Unused in RMII mode. The device uses the X1 reference clock input as the 50 MHz reference for
both transmit and receive.
SNI TRANSMIT CLOCK: 10 MHz Transmit clock output in 10 Mb SNI mode. The MAC should
source TX_EN and TXD_0 using this clock.
TX_EN I, PD 2 MII TRANSMIT ENABLE: Active high input indicates the presence of valid data inputs on
TXD[3:0].
RMII TRANSMIT ENABLE: Active high input indicates the presence of valid data on TXD[1:0].
SNI TRANSMIT ENABLE: Active high input indicates the presence of valid data on TXD_0.
6 Pin Configuration and Functions Copyright © 2007–2015, Texas Instruments Incorporated
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