Specifications

DP83848C , DP83848I
DP83848VYB, DP83848YB
SNLS266E –MAY 2007–REVISED MARCH 2015 www.ti.com
Table 6-17. Auto-Negotiation Next Page Transmit Register (ANNPTR), address 0x07h (continued)
Bit Bit Name Default Description
10:0 CODE <000 0000 0001>, RW Code:
This field represents the code field of the next page transmission. If the MP bit is
set (bit 13 of this register), then the code shall be interpreted as a "Message
Page”, as defined in annex 28C of IEEE 802.3. Otherwise, the code shall be
interpreted as an "Unformatted Page”, and the interpretation is application
specific.
The default value of the CODE represents a Null Page as defined in Annex 28C
of IEEE 802.3.
6.6.1.2 Extended Registers
6.6.1.2.1 PHY Status Register (PHYSTS)
This register provides a single location within the register set for quick access to commonly accessed
information.
Table 6-18. PHY Status Register (PHYSTS), address 10h
Bit Bit Name Default Description
15 RESERVED 0, RO RESERVED: Write ignored, read as 0.
14 MDIX MODE 0, RO MDIX mode as reported by the Auto-Negotiation logic:
This bit will be affected by the settings of the MDIX_EN and FORCE_MDIX bits
in the PHYCR register. When MDIX is enabled, but not forced, this bit will
update dynamically as the Auto-MDIX algorithm swaps between MDI and MDIX
configurations.
1 = MDI pairs swapped
(Receive on TPTD pair, Transmit on TPRD pair)
0 = MDI pairs normal
(Receive on TRD pair, Transmit on TPTD pair)
13 RECEIVE ERROR 0, RO/LH Receive Error Latch:
LATCH
This bit will be cleared upon a read of the RECR register.
1 = Receive error event has occurred since last read of RXERCNT (address
15h, Page 0).
0 = No receive error event has occurred.
12 POLARITY STATUS 0, RO Polarity Status:
This bit is a duplication of bit 4 in the 10BTSCR register. This bit will be cleared
upon a read of the 10BTSCR register, but not upon a read of the PHYSTS
register.
1 = Inverted Polarity detected.
0 = Correct Polarity detected.
11 FALSE CARRIER SENSE 0, RO/LH False Carrier Sense Latch:
LATCH
This bit will be cleared upon a read of the FCSR register.
1 = False Carrier event has occurred since last read of FCSCR (address 14h).
0 = No False Carrier event has occurred.
10 SIGNAL DETECT 0, RO/LL 100Base-TX qualified Signal Detect from PMA:
This is the SD that goes into the link monitor. It is the AND of raw SD and
descrambler lock, when address 16h, bit 8 (page 0) is set. When this bit is
cleared, it will be equivalent to the raw SD from the PMD.
9 DESCRAMBLER LOCK 0, RO/LL 100Base-TX Descrambler Lock from PMD.
58 Detailed Description Copyright © 2007–2015, Texas Instruments Incorporated
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