Specifications

DP83848C , DP83848I
DP83848VYB, DP83848YB
www.ti.com SNLS266E –MAY 2007–REVISED MARCH 2015
Table 6-10. Basic Mode Status Register (BMSR), address 0x01h (continued)
Bit Bit Name Default Description
1 JABBER DETECT 0, RO/LH Jabber Detect: This bit only has meaning in 10 Mb/s mode.
1 = Jabber condition detected.
0 = No Jabber.
This bit is implemented with a latching function, such that the occurrence of a jabber
condition causes it to set until it is cleared by a read to this register by the management
interface or by a reset.
0 EXTENDED 1, RO/P Extended Capability:
CAPABILITY
1 = Extended register capabilities.
0 = Basic register set capabilities only.
The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83848VYB. The
Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), the vendor's model
number and the model revision number. A PHY may return a value of zero in each of the 32 bits of the
PHY Identifier if desired. The PHY Identifier is intended to support network management. TI's IEEE
assigned OUI is 080017h.
6.6.1.1.3 PHY Identifier Register #1 (PHYIDR1)
Table 6-11. PHY Identifier Register #1 (PHYIDR1), address 0x02h
Bit Bit Name Default Description
15:0 OUI_MSB <0010 0000 0000 OUI Most Significant Bits: Bits 3 to 18 of the OUI (080017h) are stored in bits 15
0000>, RO/P to 0 of this register. The most significant two bits of the OUI are ignored (the IEEE
standard refers to these as bits 1 and 2).
6.6.1.1.4 PHY Identifier Register #2 (PHYIDR2)
Table 6-12. PHY Identifier Register #2 (PHYIDR2), address 0x03h
Bit Bit Name Default Description
15:10 OUI_LSB <0101 11> , RO/P OUI Least Significant Bits:
Bits 19 to 24 of the OUI (080017h) are mapped from bits 15 to 10 of this register
respectively.
9:4 VNDR_MDL <00 1010>, RO/P Vendor Model Number:
The six bits of vendor model number are mapped from bits 9 to 4 (most significant bit to
bit 9).
3:0 MDL_REV <0010>, RO/P Model Revision Number:
Four bits of the vendor model revision number are mapped from bits 3 to 0 (most
significant bit to bit 3). This field will be incremented for all major device changes.
6.6.1.1.5 Auto-Negotiation Advertisement Register (ANAR)
This register contains the advertised abilities of this device as they will be transmitted to its link partner
during Auto-Negotiation.
Table 6-13. Negotiation Advertisement Register (ANAR), address 0x04h
Bit Bit Name Default Description
15 NP 0, RW Next Page Indication:
0 = Next Page Transfer not desired.
1 = Next Page Transfer desired.
14 RESERVED 0, RO/P RESERVED by IEEE: Writes ignored, Read
as 0.
Copyright © 2007–2015, Texas Instruments Incorporated Detailed Description 53
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